SM120 is the streaming multiprocessor architecture used in NVIDIA's Blackwell GPU family
(RTX 5090, GB202). It is the successor to SM100 (Blackwell server) and SM89 (Ada Lovelace).
Property
Value
Architecture
SM120 (Blackwell consumer)
CUDA Capability
12.0 (__CUDA_ARCH__ = 1200)
Reference GPU
RTX 5090 (GB202), 170 SMs
Registers per SM
65,536 × 32-bit
Shared Memory per SM
100 KB (configurable with L1)
L1 Cache per SM
128 KB (configurable with shared)
Instruction Width
128 bits (64-bit instruction + 64-bit control word)
Max Threads per Block
1024
Warp Size
32 threads
Max Warps per SM
64 (configurable by register pressure)
NVIDIA Internal Codename
“Mercury” (SASS code generator)
2. Execution Model
Each SM executes warps of 32 threads in lockstep (SIMT). The warp scheduler selects
a ready warp each cycle and dispatches one instruction. SM120 supports dual-issue of certain
instruction pairs (e.g., integer + floating-point, or integer + memory).
Divergence Handling
Structured divergence uses convergence barriers: BSSY sets a reconvergence point,
BSYNC waits for all threads in the region. SM120 has 6 barrier slots (B0–B5).
For unstructured control flow, WARPSYNC forces reconvergence.
Occupancy
Register usage determines how many warps can co-reside on an SM. With 65,536 registers and
a maximum of 255 per thread, the register pressure is the primary occupancy limiter.
NVIDIA’s compiler uses a sophisticated register target selection algorithm (947 decoded configuration knobs)
that balances register count against warp occupancy, including shared memory spilling as a
first-class strategy (RegAllocCudaSmemSpillEnable).
3. Register Files
File
Range
Width
Encoding
Description
GPR
R0–R254, RZ
32-bit
8 bits
General purpose. RZ (R255) always reads zero, writes are discarded.
Even-aligned pairs (R0:R1, R2:R3, …) for 64-bit operations (.64, .WIDE).
Quad-aligned (R0:R3, R4:R7, …) for 128-bit operations (.128).
Predicate
P0–P6, PT
1-bit
3 bits
Boolean predicates. PT (P7) is hardwired true. Used as guard predicates
(@P0 = execute if P0, @!P0 = execute if not P0) and as
carry flags for IADD3.X.
Uniform GPR
UR0–UR63, URZ
32-bit
6 bits
Warp-uniform values (same across all 32 threads). Processed by the
Uniform Datapath (UDP). Used for loop counters, addresses, descriptors.
Uniform Pred
UP0–UP6, UPT
1-bit
3 bits
Uniform predicates.
Barrier
B0–B5
—
3 bits
Convergence and dependency barriers. Allocated by the scheduler.
4. Instruction Encoding
Every SM120 instruction is exactly 128 bits (16 bytes), stored little-endian as two 64-bit words:
128-bit instruction (16 bytes, little-endian in memory)
fields[] — list of variable bitfields, each with {shift, bits, extraction}
variable_mask — OR of all field masks
To encode: instruction = and_base | (field_value & mask) << shift for each field.
Extraction Types
Type
Description
reg
GPR number (0–254, 255=RZ)
ureg
Uniform register number (0–63)
pred
Predicate register (0–6, 7=PT)
guard
Guard predicate at bits [15:12]
imm
Immediate value
imm_shrN
Immediate right-shifted by N before encoding
f32
IEEE 754 FP32 immediate
neg, inv, abs
Operand modifier flags (1-bit each)
reuse
Operand reuse hint (tells hardware to cache the value)
sysreg
Special register ID (for S2R/CS2R)
barrier
Barrier register index (B0–B5)
sub_rN, sub_urN
Sub-fields of composite address operands
cm16_off, cm17_off
Constant memory bank offset encoding
5. Control Word and Scheduling
The upper 64 bits of each instruction contain scheduling information that controls
instruction issue timing, dependency tracking, and pipeline utilization. These bits are set
by NVIDIA’s compiler or by a custom barrier insertion pass.
Bits
Field
Description
[67:64]
stall_count
Minimum cycles to wait before issuing this instruction (0–15).
[68]
yield
Yield hint. When set, suggests the scheduler switch to another warp.
[71:64]
Rc2 / sched_lo
For some formats: 8-bit Rc2 operand. Otherwise: lower scheduling byte.
[75:72]
write_barrier
Write barrier (scoreboard) index. Assigns this instruction’s result to barrier Bn.
[79:76]
read_barrier
Read barrier configuration.
[85:80]
wait_mask
6-bit wait mask. Bit N = wait for barrier BN to complete before executing.
[107]
sync_flag
Set for instructions requiring synchronization (LDC, some IADD3, EXIT).
Assign write barriers. The producer instruction sets write_barrier = Bn in its control word.
Uses interval graph coloring (like register allocation) to map live barrier ranges to B0–B5.
Set wait masks on consumers. When an instruction reads a register produced by a long-latency op,
set bit N in the consumer’s wait_mask.
The .E modifier on LDG/STG indicates “extended” 64-bit addressing.
9. Instruction Reference
Latency legend:N ★ = measured on RTX 5090 hardware (661 instructions) ·
N ~ = synthetic estimate (well-sourced but not measured) ·
N † = ptxas internal scheduler weight (not a hardware cycle count) ·
— = unknown Partial forms: 363 of 1,811 InsKeys have ? in their name,
meaning some operand types were not fully determined during bit-probing.
They have valid encodings but the SASS operand syntax is not fully known.
Collapsed by default — click to expand.
Atomic read-modify-write on global memory (ADD, MIN, MAX, CAS, EXCH, AND, OR, XOR).
InsKey
Operands
Pipeline
Latency
ATOMG.E.OR.STRONG.GPU_P_P_R_dARI_R
P_P_R_dARI_R
MEMORY
200 ~
ATOMG.E.OR.STRONG.GPU_P_P_R_dARI_R — 10 fields
and_base: 0x80010008000000000ff09a8
var_mask: 0x1c000000000e00ff7fffffffff00f004
Bits
W
Tok
Extraction
[124]
1
t3
reuse
[123]
1
t4
reuse
[122]
1
t3
reuse
[83:81]
3
t1
pred
[71:64]
8
t3
ureg
[62:40]
23
t3
imm
[39:32]
8
t4
reg
[31:24]
8
t3
reg
[15:12]
4
t0
guard
[2]
1
t0
guard
ATOMS
Atomic on shared memory.
InsKey
Operands
Modifiers
Pipeline
Latency
ATOMS_R_ARI_R
R_ARI_R
ADD, AND, EXCH, MAX,S32, OR, XOR, CAS
MEMORY_SHARED
30 ~
ATOMS_R_ARI_R_R
R_ARI_R_R
CAS, ADD, AND, EXCH, MAX,S32, OR, XOR
MEMORY_SHARED
30 ~
ATOMS_R_ARURI_R
R_ARURI_R
ADD, AND, EXCH, MAX,S32, OR, XOR, CAS
MEMORY_SHARED
30 ~
ATOMS_R_ARI_R.ADD — 5 fields · 2 samples
and_base: 0x0000000008000004000000091208798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R.AND — 5 fields · 2 samples
and_base: 0x000000000a800004000000031211798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R.EXCH — 5 fields · 2 samples
and_base: 0x000000000c0000040000000c1210798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R.MAX,S32 — 7 fields · 1 samples
and_base: 0x0000000009000200000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R.OR — 7 fields · 1 samples
and_base: 0x000000000b000000000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R.XOR — 7 fields · 1 samples
and_base: 0x000000000b800000000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R.CAS — 7 fields · 2 samples
and_base: 0x0000000000000009000000080110738d
var_mask: 0x1c000000000000ff000000ffffff0000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R_R.CAS — 7 fields · 2 samples
and_base: 0x0000000000000009000000080110738d
var_mask: 0x1c000000000000ff000000ffffff0000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R_R.ADD — 5 fields · 2 samples
and_base: 0x0000000008000004000000091208798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R_R.AND — 5 fields · 2 samples
and_base: 0x000000000a800004000000031211798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R_R.EXCH — 5 fields · 2 samples
and_base: 0x000000000c0000040000000c1210798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R_R.MAX,S32 — 7 fields · 1 samples
and_base: 0x0000000009000200000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R_R.OR — 7 fields · 1 samples
and_base: 0x000000000b000000000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARI_R_R.XOR — 7 fields · 1 samples
and_base: 0x000000000b800000000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARURI_R.ADD — 5 fields · 2 samples
and_base: 0x0000000008000004000000091208798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARURI_R.AND — 5 fields · 2 samples
and_base: 0x000000000a800004000000031211798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARURI_R.EXCH — 5 fields · 2 samples
and_base: 0x000000000c0000040000000c1210798c
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARURI_R.MAX,S32 — 7 fields · 1 samples
and_base: 0x0000000009000200000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARURI_R.OR — 7 fields · 1 samples
and_base: 0x000000000b000000000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARURI_R.XOR — 7 fields · 1 samples
and_base: 0x000000000b800000000000000000798c
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
ATOMS_R_ARURI_R.CAS — 7 fields · 2 samples
and_base: 0x0000000000000009000000080110738d
var_mask: 0x1c000000000000ff000000ffffff0000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
B2R
Read barrier count register into a GPR. Used to check if an async operation completed.
InsKey
Operands
Modifiers
Pipeline
Latency
B2R_R_P
R_P
RESULT
BARRIER
4 ~
B2R_R_P.RESULT — 5 fields · 150 samples
and_base: 0x40000000000000ff731c
var_mask: 0x1c000000000e40000000000000fff001
Bits
W
Tok
Extraction
[83:81]
3
t2
pred
[78]
1
t1
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
[0]
1
t2
pred
B2R.RESULT
Read barrier count register into a GPR. Used to check if an async operation completed.
InsKey
Operands
Pipeline
Latency
B2R.RESULT_R
R
BARRIER
4 ~
B2R.RESULT_R_P
R_P
BARRIER
4 ~
B2R.RESULT_R — 2 fields
and_base: 0xe0000000000000000031c
var_mask: 0x1c000000000000000000000000fff000
Bits
W
Tok
Extraction
[23:16]
8
t1
reg
[15:12]
4
t0
guard
B2R.RESULT_R_P — 1 fields · 32 samples
and_base: 0x00000000000040000000000000ff731c
var_mask: 0x00000000000200000000000000000000
Bits
W
Tok
Extraction
[81]
1
t2
pred
BAR
Thread block barrier. All threads in the block synchronize at this point. BAR.SYNC: basic barrier. BAR.RED: barrier with warp-level reduction (AND, OR, POPC).
Thread block barrier. All threads in the block synchronize at this point. BAR.SYNC: basic barrier. BAR.RED: barrier with warp-level reduction (AND, OR, POPC).
Thread block barrier. All threads in the block synchronize at this point. BAR.SYNC: basic barrier. BAR.RED: barrier with warp-level reduction (AND, OR, POPC).
Thread block barrier. All threads in the block synchronize at this point. BAR.SYNC: basic barrier. BAR.RED: barrier with warp-level reduction (AND, OR, POPC).
Thread block barrier. All threads in the block synchronize at this point. BAR.SYNC: basic barrier. BAR.RED: barrier with warp-level reduction (AND, OR, POPC).
InsKey
Operands
Modifiers
Pipeline
Latency
BAR.SYNC.DEFER_BLOCKING_II
BLOCKING_II
_BLOCKING
BARRIER
0 ~
BAR.SYNC.DEFER_BLOCKING_P_II
BLOCKING_P_II
—
BARRIER
0 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
BAR.SYNC.DEFER_BLOCKING_II_?
BLOCKING_II_?
BARRIER
0 ~
BAR.SYNC.DEFER_BLOCKING_II._BLOCKING — 3 fields
and_base: 0x31d
var_mask: 0x1c0000000000000003c000000000f800
Bits
W
Tok
Extraction
[57:54]
4
t1
imm
[15:12]
4
t0
guard
[11]
1
t1
imm
BAR.SYNC.DEFER_BLOCKING_P_II — 3 fields
and_base: 0x31d
var_mask: 0x1c0000000000000003c000000000f800
Bits
W
Tok
Extraction
[57:54]
4
t1
imm
[15:12]
4
t0
guard
[11]
1
t1
imm
BMSK
Bit mask generation. BMSK: generates a mask of N consecutive 1-bits. BMSK.W: wrapping variant.
InsKey
Operands
Pipeline
Latency
BMSK_R_R_R
R_R_R
INT_ARITH
4 ★
BMSK_R_R_R — 9 fields
and_base: 0x21b
var_mask: 0x1c00200000000000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[109]
1
t2
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
BMSK.W
Bit mask generation. BMSK: generates a mask of N consecutive 1-bits. BMSK.W: wrapping variant.
InsKey
Operands
Pipeline
Latency
BMSK.W_R_R_R
R_R_R
INT_ARITH
4 ★
BMSK.W_R_R_R — 6 fields
and_base: 0x21b
var_mask: 0x1c00000000000000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
BPT.TRAP
InsKey
Operands
Pipeline
Latency
BPT.TRAP_II
II
CTRL_FLOW
0 ~
BPT.TRAP_II — 2 fields
and_base: 0x300000000000040000095c
var_mask: 0x1c00000000000000000000180000f000
Bits
W
Tok
Extraction
[36:35]
2
t1
imm
[15:12]
4
t0
guard
BRA
Branch. PC-relative target. Conditional when guarded by @Px.
InsKey
Operands
Modifiers
Pipeline
Latency
BRA_II
II
CONV, DIV, U
CTRL_FLOW
0 ~
BRA_II_II
II_II
—
CTRL_FLOW
0 ~
BRA_P_II
P_II
CONV, DIV, U
CTRL_FLOW
0 ~
BRA_P_II_II
P_II_II
—
CTRL_FLOW
0 ~
BRA_P_P_II
P_P_II
—
CTRL_FLOW
0 ~
BRA_UP_II
UP_II
U, CONV, DIV
CTRL_FLOW
0 ~
BRA_UR_II
UR_II
DIV, CONV, U
CTRL_FLOW
0 ~
4 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
BRA_II_II_?
II_II_?
CTRL_FLOW
0 ~
BRA_II_II_II_?
II_II_II_?
CTRL_FLOW
0 ~
BRA_II_II_II_II_?
II_II_II_II_?
CTRL_FLOW
0 ~
BRA_P_II_II_?
P_II_II_?
CTRL_FLOW
0 ~
BRA_II_II_? — 2 fields · 32 samples
and_base: 0x00000000038000000000000000000947
var_mask: 0x000000000003fffffffffffffffcf000
Bits
W
Tok
Extraction
[81:18]
64
t1
imm
[15:12]
4
t0
guard
BRA_II_II_II_? — 2 fields · 32 samples
and_base: 0x00000000038000000000000000000947
var_mask: 0x000000000003fffffffffffffffcf000
Bits
W
Tok
Extraction
[81:18]
64
t1
imm
[15:12]
4
t0
guard
BRA_II_II_II_II_? — 2 fields · 32 samples
and_base: 0x00000000038000000000000000000947
var_mask: 0x000000000003fffffffffffffffcf000
Bits
W
Tok
Extraction
[81:18]
64
t1
imm
[15:12]
4
t0
guard
BRA_P_II_II_? — 1 fields · 32 samples
and_base: 0x000000000083fffffffffffc00008947
var_mask: 0x00000000000000000000000000fc0000
Bits
W
Tok
Extraction
[23:18]
6
t2
imm
BRA_II — 4 fields · 1,108 samples
and_base: 0x00000000038000000000000000000947
var_mask: 0x1c0000000003fffffffffffce0fcf000
Bits
W
Tok
Extraction
[81:34]
48
t0
reg
[31:29]
3
t0
reg
[23:16]
8
t1
imm
[15:12]
4
t0
guard
BRA_II.CONV — 1 fields · 3 samples
and_base: 0x00000000038000000000006310fc7947
var_mask: 0x1c000000000000000000000060000000
Bits
W
Tok
Extraction
[30:29]
2
t0
guard
BRA_II.DIV — 1 fields · 2 samples
and_base: 0x00000000038000000000005640fc7947
var_mask: 0x1c000000000000000000000030000000
Bits
W
Tok
Extraction
[29:28]
2
t1
imm_shr3
BRA_II.U — 2 fields · 4 samples
and_base: 0x00000000038000000000000100fc7947
var_mask: 0x1c000000000000000000fffcf0000000
Bits
W
Tok
Extraction
[81:34]
48
t0
[31:28]
4
t0
guard
BRA_II_II — 2 fields · 32 samples
and_base: 0x00000000038000000000000000000947
var_mask: 0x000000000003fffffffffffffffcf000
Bits
W
Tok
Extraction
[81:18]
64
t1
imm
[15:12]
4
t0
guard
BRA_P_II — 4 fields · 31 samples
and_base: 0x00000000000000000000000000000947
var_mask: 0x1c0000000383fffffffffffc00fcf000
Bits
W
Tok
Extraction
[89:87]
3
t1
pred
[81:34]
48
t0
guard_lo3
[23:16]
8
t0
[15:12]
4
t0
guard
BRA_P_II.CONV — 1 fields · 3 samples
and_base: 0x00000000038000000000006310fc7947
var_mask: 0x1c000000000000000000000060000000
Bits
W
Tok
Extraction
[30:29]
2
t0
guard
BRA_P_II.DIV — 1 fields · 2 samples
and_base: 0x00000000038000000000005640fc7947
var_mask: 0x1c000000000000000000000030000000
Bits
W
Tok
Extraction
[29:28]
2
t1
imm_shr3
BRA_P_II.U — 2 fields · 4 samples
and_base: 0x00000000038000000000000100fc7947
var_mask: 0x1c000000000000000000fffcf0000000
Bits
W
Tok
Extraction
[81:34]
48
t0
[31:28]
4
t0
guard
BRA_P_II_II — 3 fields · 32 samples
and_base: 0x00000000000000000000000000008947
var_mask: 0x000000000383fffffffffffffffc7000
Bits
W
Tok
Extraction
[89:87]
3
t1
pred
[81:18]
64
t2
imm
[14:12]
3
t0
guard
BRA_P_P_II — 5 fields
and_base: 0x947
var_mask: 0x1c0000000783fffffffffffc00fff000
Bits
W
Tok
Extraction
[90]
1
t1
neg
[89:87]
3
t1
pred
[81:34]
48
t2
imm
[23:16]
8
t2
imm
[15:12]
4
t0
guard
BRA_UP_II.U — 3 fields · 13 samples
and_base: 0x000000000b8000000000000100007547
var_mask: 0x1c0000000003fffffffffffc08fc0000
Bits
W
Tok
Extraction
[81:34]
48
t0
guard_neg
[27]
1
t1
inv
[23:16]
8
t2
imm_shr8
BRA_UP_II — 4 fields · 1,108 samples
and_base: 0x00000000038000000000000000000947
var_mask: 0x1c0000000003fffffffffffce0fcf000
Bits
W
Tok
Extraction
[81:34]
48
t0
reg
[31:29]
3
t0
reg
[23:16]
8
t1
imm
[15:12]
4
t0
guard
BRA_UP_II.CONV — 1 fields · 3 samples
and_base: 0x00000000038000000000006310fc7947
var_mask: 0x1c000000000000000000000060000000
Bits
W
Tok
Extraction
[30:29]
2
t0
guard
BRA_UP_II.DIV — 1 fields · 2 samples
and_base: 0x00000000038000000000005640fc7947
var_mask: 0x1c000000000000000000000030000000
Bits
W
Tok
Extraction
[29:28]
2
t1
imm_shr3
BRA_UR_II.DIV — 2 fields · 150 samples
and_base: 0xb8000000000000200007947
var_mask: 0x1c00000000000000000000040ffc0000
Bits
W
Tok
Extraction
[34]
1
t0
imm
[27:18]
10
t0
BRA_UR_II — 4 fields · 1,108 samples
and_base: 0x00000000038000000000000000000947
var_mask: 0x1c0000000003fffffffffffce0fcf000
Bits
W
Tok
Extraction
[81:34]
48
t0
reg
[31:29]
3
t2
imm
[23:16]
8
t1
imm
[15:12]
4
t0
guard
BRA_UR_II.CONV — 1 fields · 3 samples
and_base: 0x00000000038000000000006310fc7947
var_mask: 0x1c000000000000000000000060000000
Bits
W
Tok
Extraction
[30:29]
2
t2
guard
BRA_UR_II.U — 2 fields · 4 samples
and_base: 0x00000000038000000000000100fc7947
var_mask: 0x1c000000000000000000fffcf0000000
Bits
W
Tok
Extraction
[81:34]
48
t0
[31:28]
4
t2
imm
BRA.DIV
Branch. PC-relative target. Conditional when guarded by @Px.
InsKey
Operands
Pipeline
Latency
BRA.DIV_UR_II
UR_II
CTRL_FLOW
0 ~
BRA.DIV_UR_II — 2 fields · 32 samples
and_base: 0x000000000b8000000000000000007947
var_mask: 0x00000000000000000000001ffffc0000
Bits
W
Tok
Extraction
[28:24]
5
t1
ureg
[36:18]
19
t2
imm
BRA.U
Branch. PC-relative target. Conditional when guarded by @Px.
InsKey
Operands
Pipeline
Latency
BRA.U_UP_II
UP_II
CTRL_FLOW
0 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
BRA.U_?_II
?_II
CTRL_FLOW
0 ~
BRA.U_?_II — 1 fields · 32 samples
and_base: 0x000000000b8000000000000000007547
var_mask: 0x000000000003fffffffffffffffc0000
Bits
W
Tok
Extraction
[81:18]
64
t2
imm
BRA.U_UP_II — 1 fields · 32 samples
and_base: 0x000000000b8000000000000000007547
var_mask: 0x000000000003fffffffffffffffc0000
Bits
W
Tok
Extraction
[81:18]
64
t2
imm
BREAK
Break out of convergence barrier region.
InsKey
Operands
Modifiers
Pipeline
Latency
BREAK_B
B
RELIABLE
CTRL_FLOW
0 ~
BREAK_P_B
P_B
RELIABLE
CTRL_FLOW
0 ~
BREAK_B.RELIABLE — 2 fields · 10 samples
and_base: 0x00000000038001000000000000000942
var_mask: 0x1c00000000000000000000000003f000
Bits
W
Tok
Extraction
[19:16]
4
t1
barrier
[15:12]
4
t0
guard
BREAK_P_B.RELIABLE — 8 fields · 106 samples
and_base: 0x8001000000000000018942
var_mask: 0x1c0000000380010000000000000ff040
Bits
W
Tok
Extraction
[90]
1
t1
neg
[89:87]
3
t1
pred
[72]
1
t1
pred
[19:16]
4
t1
pred
[15:12]
4
t0
guard
[6]
1
t1
pred
[4:2]
3
t0
imm
[0]
1
t0
imm
BREAK.RELIABLE
Break out of convergence barrier region.
InsKey
Operands
Pipeline
Latency
BREAK.RELIABLE_II
II
CTRL_FLOW
0 ~
BREAK.RELIABLE_P_B
P_B
CTRL_FLOW
0 ~
BREAK.RELIABLE_II — 2 fields · 32 samples
and_base: 0x00000000038001000000000000000942
var_mask: 0x00000000000000000000000000038000
Bits
W
Tok
Extraction
[17:16]
2
t1
imm
[15]
1
t0
guard
BREV
Bit reverse (reflect all 32 bits).
InsKey
Operands
Pipeline
Latency
BREV_R_R
R_R
INT_ARITH
8 ★
BREV_R_R — 3 fields
and_base: 0x00000000000000000000000000007301
var_mask: 0x1ffffe0000000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
BRX
Indirect branch via register.
InsKey
Operands
Pipeline
Latency
BRX_II
II
CTRL_FLOW
0 ~
BRX_L
L
CTRL_FLOW
0 ~
BRX_II — 2 fields · 32 samples
and_base: 0x000000000383ffffffffffc000007949
var_mask: 0x00000000000000000000003ffffc0000
Bits
W
Tok
Extraction
[28:25]
4
t1
reg
[37:18]
20
t1
imm
BRX_L — 4 fields · 62 samples
and_base: 0x000000000383ffffffffff8000007949
var_mask: 0x1c000000000000000000007cfffc0000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[81:34]
48
t2
imm_shr16
[31:24]
8
t1
reg
[23:16]
8
t0
guard_neg
BRXU
Indirect branch via uniform register.
InsKey
Operands
Pipeline
Latency
BRXU_II
II
CTRL_FLOW
0 ~
BRXU_L
L
CTRL_FLOW
0 ~
BRXU_II — 2 fields · 2 samples
and_base: 0x000000000b83fffffffffe0000047958
var_mask: 0x0000000000000000000000fffff80000
Bits
W
Tok
Extraction
[28:26]
3
t1
ureg
[39:19]
21
t1
imm
BRXU_L — 4 fields · 8 samples
and_base: 0x000000000b83fffffffffe0000007958
var_mask: 0x1c00000000000000000001fcfffc0000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[81:34]
48
t0
[31:24]
8
t1
ureg
[23:16]
8
t0
BSSY
Set convergence barrier. Marks the re-convergence point for a divergent region. A barrier slot (B0–B5) is allocated. Paired with BSYNC.
InsKey
Operands
Modifiers
Pipeline
Latency
BSSY_B_II
B_II
RECONVERGENT, RELIABLE
CTRL_FLOW
0 ~
BSSY_II_II
II_II
—
CTRL_FLOW
0 ~
BSSY_B_II — 2 fields · 8 samples
and_base: 0x00000000038000000001000000067945
var_mask: 0x1c000000000000000002fff000010000
Bits
W
Tok
Extraction
[63:34]
30
t0
[19:16]
4
t1
barrier
BSSY_B_II.RECONVERGENT — 2 fields · 350 samples
and_base: 0x00000000038002000000000000007945
var_mask: 0x1c000000000000000007fff000070000
Bits
W
Tok
Extraction
[63:34]
30
t0
[19:16]
4
t1
barrier
BSSY_B_II.RELIABLE — 2 fields · 7 samples
and_base: 0x38001000000000000007945
var_mask: 0xfffffe0000000000fffffffc000f0000
Bits
W
Tok
Extraction
[63:34]
30
t0
[19:16]
4
t1
barrier
BSSY_II_II — 2 fields · 32 samples
and_base: 0x00000000038000000000000000007945
var_mask: 0x00000000000000000001fff000030000
Bits
W
Tok
Extraction
[48:36]
13
t2
imm
[17:16]
2
t1
imm
BSSY.RECONVERGENT
Set convergence barrier. Marks the re-convergence point for a divergent region. A barrier slot (B0–B5) is allocated. Paired with BSYNC.
InsKey
Operands
Pipeline
Latency
BSSY.RECONVERGENT_II_II
II_II
CTRL_FLOW
0 ~
BSSY.RECONVERGENT_II_II — 2 fields · 32 samples
and_base: 0x00000000038002000000000000007945
var_mask: 0x00000000000000000001fff000070000
Bits
W
Tok
Extraction
[48:36]
13
t2
imm
[18:16]
3
t1
imm
BSSY.RELIABLE
Set convergence barrier. Marks the re-convergence point for a divergent region. A barrier slot (B0–B5) is allocated. Paired with BSYNC.
InsKey
Operands
Pipeline
Latency
BSSY.RELIABLE_II_II
II_II
CTRL_FLOW
0 ~
BSSY.RELIABLE_II_II — 2 fields · 32 samples
and_base: 0x00000000038001000000000000007945
var_mask: 0x000000000000000000003ff000010000
Bits
W
Tok
Extraction
[45:36]
10
t2
imm
[16]
1
t1
imm
BSYNC
Synchronize at convergence barrier. Waits until all diverged threads have finished their paths.
InsKey
Operands
Modifiers
Pipeline
Latency
BSYNC_B
B
RECONVERGENT, RELIABLE
CTRL_FLOW
0 ~
BSYNC_B_B
B_B
—
CTRL_FLOW
0 ~
BSYNC_II
II
—
CTRL_FLOW
0 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
BSYNC_B_II_?
B_II_?
CTRL_FLOW
0 ~
BSYNC_B — 1 fields · 3 samples
and_base: 0x00000000038000000000000000067941
var_mask: 0x1c000000000000000000000000010000
Bits
W
Tok
Extraction
[19:16]
4
t1
barrier
BSYNC_B.RECONVERGENT — 1 fields · 9 samples
and_base: 0x00000000038002000000000000007941
var_mask: 0x1c000000000000000000000000070000
Bits
W
Tok
Extraction
[19:16]
4
t1
barrier
BSYNC_B.RELIABLE — 1 fields · 5 samples
and_base: 0x00000000038001000000000000007941
var_mask: 0x1c000000000000000000000000030000
Bits
W
Tok
Extraction
[19:16]
4
t1
barrier
BSYNC_B_B — 1 fields · 1 samples
and_base: 0x00000000038000000000000000007941
var_mask: 0x1c000000000000000000000000010000
Bits
W
Tok
Extraction
[19:16]
4
t1
barrier
BSYNC_II — 1 fields · 32 samples
and_base: 0x00000000038000000000000000007941
var_mask: 0x00000000000000000000000000030000
Bits
W
Tok
Extraction
[17:16]
2
t1
imm
BSYNC.RECONVERGENT
Synchronize at convergence barrier. Waits until all diverged threads have finished their paths.
InsKey
Operands
Pipeline
Latency
BSYNC.RECONVERGENT_II
II
CTRL_FLOW
0 ~
BSYNC.RECONVERGENT_II_II
II_II
CTRL_FLOW
0 ~
3 partial encodings — operand types not fully identified
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
ENDCOLLECTIVE_?_?
?_?
INT_ARITH
6 ~
ENDCOLLECTIVE — 6 fields · 150 samples
and_base: 0x3800000000000000000791b
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[90:87]
4
t0
imm
[15:12]
4
t0
guard
[8]
1
t0
imm
[6]
1
t0
[3]
1
t0
imm
[1:0]
2
t0
imm
ERRBAR
InsKey
Operands
Pipeline
Latency
ERRBAR
BARRIER
0 ~
ERRBAR — 2 fields · 150 samples
and_base: 0x79ab
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
[2]
1
t0
EXIT
Terminate thread execution.
InsKey
Operands
Pipeline
Latency
EXIT
CTRL_FLOW
0 ~
EXIT_P
P
CTRL_FLOW
0 ~
4 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
EXIT_P_?
P_?
CTRL_FLOW
0 ~
EXIT_P_II_?
P_II_?
CTRL_FLOW
0 ~
EXIT_P_II_II_?
P_II_II_?
CTRL_FLOW
0 ~
EXIT_P_II_II_II_?
P_II_II_II_?
CTRL_FLOW
0 ~
EXIT_P_? — 1 fields · 32 samples
and_base: 0x0000000003800000000000000000094d
var_mask: 0x0000000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
EXIT_P_II_? — 1 fields · 32 samples
and_base: 0x0000000003800000000000000000094d
var_mask: 0x0000000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
EXIT_P_II_II_? — 1 fields · 32 samples
and_base: 0x0000000003800000000000000000094d
var_mask: 0x0000000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
EXIT_P_II_II_II_? — 1 fields · 32 samples
and_base: 0x0000000003800000000000000000094d
var_mask: 0x00000000000000000000000000001000
Bits
W
Tok
Extraction
[12]
1
t0
guard
EXIT — 1 fields · 16 samples
and_base: 0x0000000003800000000000000000094d
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
F2F
Float-to-float precision conversion.
InsKey
Operands
Modifiers
Pipeline
Latency
F2F_R_R
R_R
F32,F64
FP_ARITH
8 ★
F2F_R_R.F32,F64 — 3 fields · 3 samples
and_base: 0x00000000003010000000000800087310
var_mask: 0x1c00000000000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
F2F.BF16.F32
Float-to-float precision conversion.
InsKey
Operands
Pipeline
Latency
F2F.BF16.F32_R_R
R_R
FP_ARITH
4 ~
F2F.BF16.F32_R_R — 3 fields · 32 samples
and_base: 0x00000000002020000000000000000304
var_mask: 0x00000000000000008000001f001ff000
Bits
W
Tok
Extraction
[36:32]
5
t2
reg
[20:16]
5
t1
reg
[15:12]
4
t0
guard
F2F.F16.F32
Float-to-float precision conversion.
InsKey
Operands
Pipeline
Latency
F2F.F16.F32_R_R
R_R
FP_ARITH
8 ★
F2F.F16.F32_R_R — 2 fields · 32 samples
and_base: 0x00000000002008000000000000007304
var_mask: 0x00000000000000004000001f001f0000
Bits
W
Tok
Extraction
[36:32]
5
t2
reg
[20:16]
5
t1
reg
F2F.F32.F64
Float-to-float precision conversion.
InsKey
Operands
Pipeline
Latency
F2F.F32.F64_R_R
R_R
FP_ARITH
4 ~
F2F.F32.F64_R_R — 2 fields · 32 samples
and_base: 0x00000000003010000000000000007310
var_mask: 0x00000000000000000000003e001f0000
Bits
W
Tok
Extraction
[37:33]
5
t2
reg
[20:16]
5
t1
reg
F2F.F64.F32
Float-to-float precision conversion.
InsKey
Operands
Pipeline
Latency
F2F.F64.F32_R_R
R_R
FP_ARITH
4 ~
F2F.F64.F32_R_R_R
R_R_R
FP_ARITH
4 ~
F2F.F64.F32_R_R — 2 fields · 32 samples
and_base: 0x00000000002018000000000000007310
var_mask: 0x00000000000000000000003f003e0000
Bits
W
Tok
Extraction
[37:32]
6
t2
reg
[21:17]
5
t1
reg
F2F.F64.F32_R_R_R — 2 fields · 21 samples
and_base: 0x00000000002018000000000000007310
var_mask: 0x00000000000000000000001f003e0000
Bits
W
Tok
Extraction
[36:32]
5
t2
reg
[21:17]
5
t1
reg
F2FP
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
InsKey
Operands
Modifiers
Pipeline
Latency
F2FP.BF16.F32.PACK_AB_P_R_R_R
AB_P_R_R_R
—
FP_ARITH
4 ~
F2FP.BF16.F32.PACK_AB_R_R_R
AB_R_R_R
_AB
FP_ARITH
4 ~
1 partial encoding — operand types not fully identified
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
InsKey
Operands
Pipeline
Latency
F2FP.F16.F32.MERGE_C_P_R_R_R
C_P_R_R_R
FP_ARITH
4 ~
F2FP.F16.F32.MERGE_C_R_R_R
C_R_R_R
FP_ARITH
4 ~
F2FP.F16.F32.MERGE_C_P_R_R_R — 3 fields
and_base: 0xfe20000004000000000000000f23e
Bits
W
Tok
Extraction
[71:64]
8
t3
reg
[39:32]
8
t2
reg
[23:16]
8
t1
reg
F2FP.F16.F32.MERGE_C_R_R_R — 3 fields
and_base: 0xfe20000004000000000000000723e
Bits
W
Tok
Extraction
[71:64]
8
t3
reg
[39:32]
8
t2
reg
[23:16]
8
t1
reg
F2FP.F16.F32.PACK
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
InsKey
Operands
Modifiers
Pipeline
Latency
F2FP.F16.F32.PACK_AB_P0_R_R_R
AB_P0_R_R_R
—
FP_ARITH
4 ~
F2FP.F16.F32.PACK_AB_P2_R_R_R
AB_P2_R_R_R
—
FP_ARITH
4 ~
F2FP.F16.F32.PACK_AB_P5_R_R_R
AB_P5_R_R_R
—
FP_ARITH
4 ~
F2FP.F16.F32.PACK_AB_P_R_R_R
AB_P_R_R_R
—
FP_ARITH
4 ~
F2FP.F16.F32.PACK_AB_R_R_R
AB_R_R_R
_AB
FP_ARITH
4 ~
1 partial encoding — operand types not fully identified
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
InsKey
Operands
Modifiers
Pipeline
Latency
F2FP.RELU.BF16.F32.PACK_AB_P_R_R_R
AB_P_R_R_R
—
FP_ARITH
4 ~
F2FP.RELU.BF16.F32.PACK_AB_R_R_R
AB_R_R_R
_AB
FP_ARITH
4 ~
F2FP.RELU.BF16.F32.PACK_AB_P_R_R_R — 6 fields
and_base: 0x0000000000001800000000000000023e
var_mask: 0xc00000000000000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[122]
1
t2
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
F2FP.RELU.BF16.F32.PACK_AB_R_R_R._AB — 6 fields
and_base: 0x0000000000001800000000000000023e
var_mask: 0xc00000000000000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[122]
1
t2
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
F2FP.RELU.F16.F32.PACK
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
InsKey
Operands
Modifiers
Pipeline
Latency
F2FP.RELU.F16.F32.PACK_AB_P_R_R_R
AB_P_R_R_R
—
FP_ARITH
4 ~
F2FP.RELU.F16.F32.PACK_AB_R_R_R
AB_R_R_R
_AB
FP_ARITH
4 ~
F2FP.RELU.F16.F32.PACK_AB_P_R_R_R — 11 fields
and_base: 0x0000000000000800000000000000023c
var_mask: 0x1c000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
reuse
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
F2FP.RELU.F16.F32.PACK_AB_R_R_R._AB — 6 fields
and_base: 0x0000000000000800000000000000023e
var_mask: 0xc00000000000000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[122]
1
t2
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
F2FP.SATFINITE.BF16.F32.PACK
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
Float-to-float precision conversion with packing. Converts FP32 inputs to FP16, BF16, or FP8 (E4M3/E5M2) format. .PACK_AB packs two FP32 values into one FP16 register pair. .MERGE_C blends with an existing packed value. Used in quantization pipelines before QMMA.
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
IABS_R_R_?
R_R_?
INT_ARITH
4 ★
IABS_R_R — 3 fields
and_base: 0x00000000000000000000000000007213
var_mask: 0x1ffffe0000000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
IABS_R_R_R — 3 fields · 1 samples
and_base: 0x00000000000000000000000000007213
var_mask: 0x1ffffe0000000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
IADD
2-input integer add.
InsKey
Operands
Modifiers
Pipeline
Latency
IADD_P0_R_R_II
P0_R_R_II
—
INT_ARITH
4 ~
IADD_P_R_R_II
P_R_R_II
—
INT_ARITH
4 ~
IADD_P_R_R_R
P_R_R_R
—
INT_ARITH
4 ~
IADD_R_P_R_II
R_P_R_II
64,X, X, 64
INT_ARITH
4 ~
IADD_R_P_R_II_P
R_P_R_II_P
64,X, X, 64
INT_ARITH
4 ~
IADD_R_P_R_R
R_P_R_R
64, 64,X, X
INT_ARITH
4 ~
IADD_R_P_R_R_P
R_P_R_R_P
64,X, X, 64
INT_ARITH
4 ~
IADD_R_P_R_UR
R_P_R_UR
64, 64,X, X
INT_ARITH
4 ~
IADD_R_P_R_UR_P
R_P_R_UR_P
X, 64,X, 64
INT_ARITH
4 ~
IADD_R_R_II
R_R_II
64, 64,X, X
INT_ARITH
4 ~
IADD_R_R_II_P
R_R_II_P
64,X, X, 64
INT_ARITH
4 ~
IADD_R_R_R
R_R_R
64, 64,X, X
INT_ARITH
4 ~
IADD_R_R_R_II
R_R_R_II
—
INT_ARITH
4 ~
IADD_R_R_R_P
R_R_R_P
64,X, X, 64
INT_ARITH
4 ~
IADD_R_R_UR
R_R_UR
64, 64,X, X
INT_ARITH
4 ~
IADD_R_R_UR_P
R_R_UR_P
X, 64,X, 64
INT_ARITH
4 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
IADD_R_P_R_R_?
R_P_R_R_?
INT_ARITH
4 ~
IADD_P0_R_R_II — 5 fields
and_base: 0x78e00000000000000000835
var_mask: 0x100fffffffffffff000
Bits
W
Tok
Extraction
[72]
1
t2
neg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_P_R_R_II — 5 fields
and_base: 0x78e00000000000000000835
var_mask: 0x1c00000000000100fffffffffffff000
Bits
W
Tok
Extraction
[72]
1
t2
neg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_P_R_R_R — 8 fields
and_base: 0x78e00000000000000000235
var_mask: 0x1c00000000000100800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[122]
1
t2
neg
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_P_R_II — 5 fields · 5 samples
and_base: 0x00000000078000000000000100027835
var_mask: 0x1c000000000e0000fffffffeffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_II.64,X — 8 fields
and_base: 0x00000000000006000000000000000835
var_mask: 0x1ffffe00038e0100fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[72]
1
t2
neg
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_P_R_II.X — 6 fields · 6 samples
and_base: 0x0000000000000400000000005f407835
var_mask: 0x1c000000038e0000ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_II.64 — 12 fields
and_base: 0x00000000040002000000000000000235
var_mask: 0x1ffffe00038e01ff800000fffffff000
Bits
W
Tok
Extraction
[124]
1
t0
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[72]
1
t3
neg
[71:64]
8
t0
reg
[63]
1
t4
neg
[39:32]
8
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_P_R_II_P.64,X — 6 fields · 2 samples
and_base: 0x6000000000000107835
var_mask: 0xfffffe00038e0000ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_II_P.X — 6 fields · 6 samples
and_base: 0x0000000000000400000000005f407835
var_mask: 0x1c000000038e0000ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_II_P — 5 fields · 5 samples
and_base: 0x00000000078000000000000100027835
var_mask: 0x1c000000000e0000fffffffeffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_II_P.64 — 6 fields · 3 samples
and_base: 0x00000000078002000000000000ff7235
var_mask: 0x1c000000000e0100000000ffff000000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[83:81]
3
t2
pred
[72]
1
t3
neg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
IADD_R_P_R_R — 7 fields · 7 samples
and_base: 0x00000000078000000000000000007235
var_mask: 0x1c000000000e0000800000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t3
reuse
[83:81]
3
t2
pred
[63]
1
t4
neg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_R.64 — 7 fields · 3 samples
and_base: 0x00000000078002000000000000ff7235
var_mask: 0x1c000000000e0100800000ffff000000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[83:81]
3
t2
pred
[72]
1
t3
neg
[63]
1
t4
neg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
IADD_R_P_R_R.64,X — 4 fields · 2 samples
and_base: 0x0000000000000600ffffffff40547835
var_mask: 0x1c000000000e000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_R.X — 6 fields · 6 samples
and_base: 0x0000000000000400000000005f407835
var_mask: 0x1c000000038e0000ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_R_P.64,X — 12 fields
and_base: 0x00000000000006000000000000000235
var_mask: 0x1ffffe00038e01ff800000fffffff000
Bits
W
Tok
Extraction
[124]
1
t0
reuse
[123]
1
t4
reuse
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[72]
1
t3
inv
[71:64]
8
t0
reg
[63]
1
t4
inv
[39:32]
8
t4
reg
[31:24]
8
t3
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_P_R_R_P.X — 8 fields · 10 samples
and_base: 0x00000000000004000000000000007235
var_mask: 0x1c000000038e0000800000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63]
1
t4
inv
[39:32]
8
t4
reg
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_R_P — 5 fields · 5 samples
and_base: 0x00000000078000000000000100027835
var_mask: 0x1c000000000e0000fffffffeffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_R_P.64 — 7 fields · 3 samples
and_base: 0x00000000040002000000000000ff7235
var_mask: 0x1c000000038e0100000000ffff000000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[72]
1
t3
neg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
IADD_R_P_R_UR — 3 fields · 2 samples
and_base: 0x000000000f80000000000004ffff7c35
var_mask: 0x1c000000000e0000000000ff00000000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[83:81]
3
t2
pred
[39:32]
8
t4
ureg
IADD_R_P_R_UR.64 — 10 fields
and_base: 0x000000000c0002000000000000000c35
var_mask: 0x1ffffe00038e0100800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[72]
1
t3
neg
[63]
1
t4
neg
[39:32]
8
t4
ureg
[31:24]
8
t3
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_P_R_UR.64,X — 5 fields · 2 samples
and_base: 0x0000000000000600ffffffff40547835
var_mask: 0x1c000000038e000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_UR.X — 6 fields · 6 samples
and_base: 0x0000000000000400000000005f407835
var_mask: 0x1c000000038e0000ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_UR_P.X — 7 fields · 6 samples
and_base: 0x00000000080004000000000004007c35
var_mask: 0x1c000000038e0000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[39:32]
8
t4
ureg
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_UR_P — 5 fields · 5 samples
and_base: 0x00000000078000000000000100027835
var_mask: 0x1c000000000e0000fffffffeffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_UR_P.64,X — 4 fields · 2 samples
and_base: 0x0000000000000600ffffffff40547835
var_mask: 0x1c000000000e000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_P_R_UR_P.64 — 6 fields · 3 samples
and_base: 0x00000000078002000000000000ff7235
var_mask: 0x1c000000000e0100000000ffff000000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[83:81]
3
t2
pred
[72]
1
t3
neg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
IADD_R_R_II — 6 fields · 9 samples
and_base: 0x00000000078e00000000000000003835
var_mask: 0x1c00000000000100fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[72]
1
t2
neg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_R_II.64 — 5 fields · 62 samples
and_base: 0x00000000078e02000000000000000835
var_mask: 0x1c00000000000000fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_R_II.64,X — 4 fields · 2 samples
and_base: 0x0000000000000600ffffffff40547835
var_mask: 0x1c000000000e000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_II.X — 6 fields · 6 samples
and_base: 0x0000000000000400000000005f407835
var_mask: 0x1c000000038e0000ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_II_P.64,X — 6 fields · 1 samples
and_base: 0x00000000000e06000000000000007835
var_mask: 0x1c00000003800100ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[89:87]
3
t4
pred
[72]
1
t2
neg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
IADD_R_R_II_P.X — 4 fields · 4 samples
and_base: 0x00000000000e0400ffffffff53007835
var_mask: 0x1c0000000380000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[89:87]
3
t4
pred
[31:24]
8
t2
reg
[23:16]
8
t1
reg
IADD_R_R_II_P — 5 fields · 5 samples
and_base: 0x00000000078000000000000100027835
var_mask: 0x1c000000000e0000fffffffeffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_II_P.64 — 6 fields · 3 samples
and_base: 0x00000000078002000000000000ff7235
var_mask: 0x1c000000000e0100000000ffff000000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[83:81]
3
t2
pred
[72]
1
t3
neg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
IADD_R_R_R — 8 fields · 10 samples
and_base: 0x00000000078e00000000000000000235
var_mask: 0x1c00000000000100800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_R_R.64 — 10 fields · 4,170 samples
and_base: 0x00000000078e02000000000000000235
var_mask: 0x1c000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[124]
1
t0
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[72]
1
t2
neg
[71:64]
8
t0
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_R_R.64,X — 4 fields · 2 samples
and_base: 0x0000000000000600ffffffff40547835
var_mask: 0x1c000000000e000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_R.X — 6 fields · 6 samples
and_base: 0x0000000000000400000000005f407835
var_mask: 0x1c000000038e0000ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_R_II — 12 fields · 1 samples
and_base: 0x00000000040000007fffff0000000835
var_mask: 0x1ffffe00038e01ff800000fffffff000
Bits
W
Tok
Extraction
[124]
1
t0
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[72]
1
t3
neg
[71:64]
8
t0
reg
[63]
1
t4
neg
[39:32]
8
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_R_R_P.64,X — 8 fields · 1 samples
and_base: 0x00000000000e06000000000000007235
var_mask: 0x1c00000003800100800000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[89:87]
3
t4
pred
[72]
1
t2
inv
[63]
1
t3
inv
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
IADD_R_R_R_P.X — 7 fields · 9 samples
and_base: 0x00000000000e04000000000000007235
var_mask: 0x1c00000003800000800000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t2
reuse
[89:87]
3
t4
pred
[63]
1
t3
inv
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
IADD_R_R_R_P — 5 fields · 5 samples
and_base: 0x00000000078000000000000100027835
var_mask: 0x1c000000000e0000fffffffeffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_R_P.64 — 6 fields · 3 samples
and_base: 0x00000000078002000000000000ff7235
var_mask: 0x1c000000000e0100000000ffff000000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[83:81]
3
t2
pred
[72]
1
t3
neg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
IADD_R_R_UR — 7 fields · 2 samples
and_base: 0x000000000f8e00000000000418181c35
var_mask: 0x1c00000000000000800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[63]
1
t3
neg
[39:32]
8
t3
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_R_UR.64 — 8 fields · 313 samples
and_base: 0x000000000f8e02000000000000000c35
var_mask: 0x1c00000000000100800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD_R_R_UR.64,X — 4 fields · 2 samples
and_base: 0x0000000000000600ffffffff40547835
var_mask: 0x1c000000000e000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_UR.X — 6 fields · 6 samples
and_base: 0x0000000000000400000000005f407835
var_mask: 0x1c000000038e0000ffffffffffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_UR_P.X — 6 fields · 3 samples
and_base: 0x00000000080e04000000000111117c35
var_mask: 0x1c00000003800000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t1
reuse
[89:87]
3
t4
pred
[39:32]
8
t3
ureg
[31:24]
8
t1
reg
[23:16]
8
t1
reg
IADD_R_R_UR_P — 5 fields · 5 samples
and_base: 0x00000000078000000000000100027835
var_mask: 0x1c000000000e0000fffffffeffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_UR_P.64,X — 4 fields · 2 samples
and_base: 0x0000000000000600ffffffff40547835
var_mask: 0x1c000000000e000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[83:81]
3
t2
pred
[31:24]
8
t3
reg
[23:16]
8
t1
reg
IADD_R_R_UR_P.64 — 6 fields · 3 samples
and_base: 0x00000000078002000000000000ff7235
var_mask: 0x1c000000000e0100000000ffff000000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[83:81]
3
t2
pred
[72]
1
t3
neg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
IADD.64
2-input integer add.
InsKey
Operands
Pipeline
Latency
IADD.64_R_P_R_R
R_P_R_R
INT_ARITH
4 ~
IADD.64_R_P_R_R_R
R_P_R_R_R
INT_ARITH
4 ~
IADD.64_R_P_R_UR
R_P_R_UR
INT_ARITH
4 ~
IADD.64_R_R_II
R_R_II
INT_ARITH
4 ~
IADD.64_R_R_II_II
R_R_II_II
INT_ARITH
4 ~
IADD.64_R_R_R
R_R_R
INT_ARITH
4 ~
IADD.64_R_R_R_R
R_R_R_R
INT_ARITH
4 ~
IADD.64_R_R_UR
R_R_UR
INT_ARITH
4 ~
IADD.64_R_R_UR_UR
R_R_UR_UR
INT_ARITH
4 ~
7 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
IADD.64_R_R_II_II_?
R_R_II_II_?
INT_ARITH
4 ~
IADD.64_R_R_II_II_II_?
R_R_II_II_II_?
INT_ARITH
4 ~
IADD.64_R_R_R_II_?
R_R_R_II_?
INT_ARITH
4 ~
IADD.64_R_R_R_II_II_?
R_R_R_II_II_?
INT_ARITH
4 ~
IADD.64_R_R_UR_II_?
R_R_UR_II_?
INT_ARITH
4 ~
IADD.64_R_R_UR_II_II_?
R_R_UR_II_II_?
INT_ARITH
4 ~
IADD.64_R_R_UR_II_II_II_?
R_R_UR_II_II_II_?
INT_ARITH
4 ~
IADD.64_R_R_II_II_? — 3 fields · 32 samples
and_base: 0x00000000078e02000000000000007835
var_mask: 0x00000000000000000000003f7e3e0000
Bits
W
Tok
Extraction
[37:32]
6
t3
imm
[30:25]
6
t2
reg
[21:17]
5
t1
reg
IADD.64_R_R_II_II_II_? — 3 fields · 32 samples
and_base: 0x00000000078e02000000000000007835
var_mask: 0x000000000000000000000fff7e3e0000
Bits
W
Tok
Extraction
[43:32]
12
t3
imm
[30:25]
6
t2
reg
[21:17]
5
t1
reg
IADD.64_R_R_R_II_? — 4 fields · 32 samples
and_base: 0x00000000078e02000000000000000235
var_mask: 0x00000000000000000000007e7e7e7000
Bits
W
Tok
Extraction
[38:33]
6
t3
reg
[30:25]
6
t2
reg
[22:17]
6
t1
reg
[14:12]
3
t0
guard
IADD.64_R_R_R_II_II_? — 9 fields · 1 samples
and_base: 0x00000000078e02000000000000000235
var_mask: 0x1c00000000000100800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD.64_R_R_UR_II_? — 3 fields · 32 samples
and_base: 0x000000000f8e03000000000800007c35
var_mask: 0x0000000000000000000000063e7e0000
Bits
W
Tok
Extraction
[34:33]
2
t3
ureg
[29:25]
5
t2
reg
[22:17]
6
t1
reg
IADD.64_R_R_UR_II_II_? — 3 fields · 32 samples
and_base: 0x00000000078e02000000000000007035
var_mask: 0x00000000080000000000003e7e3e0e00
Bits
W
Tok
Extraction
[37:33]
5
t3
ureg
[30:25]
6
t2
reg
[21:17]
5
t1
reg
IADD.64_R_R_UR_II_II_II_? — 4 fields · 14 samples
and_base: 0x00000000078e02000000000000000035
var_mask: 0x00000000080000000000003e7e1e7e00
Bits
W
Tok
Extraction
[37:33]
5
t3
ureg
[30:25]
6
t2
reg
[20:17]
4
t1
reg
[14:12]
3
t0
guard
IADD.64_R_P_R_R — 3 fields · 32 samples
and_base: 0x00000000078002000000000000ff7235
var_mask: 0x00000000000600000000003e3e000000
Bits
W
Tok
Extraction
[82:81]
2
t2
pred
[37:33]
5
t4
reg
[29:25]
5
t3
reg
IADD.64_R_P_R_R_R — 2 fields · 19 samples
and_base: 0x00000000078002000000000000ff7235
var_mask: 0x00000000000000000000001c1e000000
Bits
W
Tok
Extraction
[36:34]
3
t4
reg
[28:25]
4
t3
reg
IADD.64_R_P_R_UR — 3 fields · 32 samples
and_base: 0x00000000078002000000000000ff7035
var_mask: 0x00000000080600008000003e7e000e00
Bits
W
Tok
Extraction
[82:81]
2
t2
pred
[37:33]
5
t4
ureg
[30:25]
6
t3
reg
IADD.64_R_R_II — 7 fields
and_base: 0x78e00000000000000000835
var_mask: 0x1c00000000000100fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t2
neg
[122]
1
t2
reuse
[72]
1
t2
neg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD.64_R_R_II_II — 3 fields · 32 samples
and_base: 0x00000000078e02000000000000007835
var_mask: 0x0000000000000000000000f8fe1e0000
Bits
W
Tok
Extraction
[39:35]
5
t3
imm
[31:25]
7
t2
reg
[20:17]
4
t1
reg
IADD.64_R_R_R — 8 fields
and_base: 0x78e00000000000000000235
var_mask: 0x1c00000000000100800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD.64_R_R_R_R — 3 fields · 32 samples
and_base: 0x00000000078e02000000000000007235
var_mask: 0x0000000000000000000000fe3e3e0000
Bits
W
Tok
Extraction
[39:33]
7
t3
reg
[29:25]
5
t2
reg
[21:17]
5
t1
reg
IADD.64_R_R_UR — 9 fields
and_base: 0xf8e00000000000000000c35
var_mask: 0x1c00000000000100800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD.64_R_R_UR_UR — 3 fields · 32 samples
and_base: 0x00000000078e02000000000000007035
var_mask: 0x0000000008000000000000fefefe0e00
Bits
W
Tok
Extraction
[39:33]
7
t3
ureg
[31:25]
7
t2
reg
[23:17]
7
t1
reg
IADD.64.X
2-input integer add.
InsKey
Operands
Pipeline
Latency
IADD.64.X_R_P_R_II_P
R_P_R_II_P
INT_ARITH
4 ~
IADD.64.X_R_P_R_R_P
R_P_R_R_P
INT_ARITH
4 ~
IADD.64.X_R_R_II_P
R_R_II_P
INT_ARITH
4 ~
IADD.64.X_R_R_R_P
R_R_R_P
INT_ARITH
4 ~
IADD.64.X_R_P_R_II_P — 5 fields · 32 samples
and_base: 0x00000000000006008000000000007035
var_mask: 0x00000000008200007fffffff1e3e0a00
Bits
W
Tok
Extraction
[87]
1
t5
pred
[81]
1
t2
pred
[62:32]
31
t4
imm
[28:25]
4
t3
reg
[21:17]
5
t1
reg
IADD.64.X_R_P_R_R_P — 5 fields · 32 samples
and_base: 0x00000000000006000000000000007235
var_mask: 0x00000000018600000000003eff3e0000
Bits
W
Tok
Extraction
[88:87]
2
t5
pred
[82:81]
2
t2
pred
[37:33]
5
t4
reg
[31:24]
8
t3
reg
[21:17]
5
t1
reg
IADD.64.X_R_R_II_P — 4 fields · 32 samples
and_base: 0x00000000000e06008000000000007035
var_mask: 0x00000000018000007fffffff3e3e0a00
Bits
W
Tok
Extraction
[88:87]
2
t4
pred
[62:32]
31
t3
imm
[29:25]
5
t2
reg
[21:17]
5
t1
reg
IADD.64.X_R_R_R_P — 4 fields · 32 samples
and_base: 0x00000000000e06000000000000007235
var_mask: 0x00000000018000000000007eff3e0000
Bits
W
Tok
Extraction
[88:87]
2
t4
pred
[38:33]
6
t3
reg
[31:24]
8
t2
imm
[21:17]
5
t1
reg
IADD.X
2-input integer add.
InsKey
Operands
Pipeline
Latency
IADD.X_R_P_R_II_P
R_P_R_II_P
INT_ARITH
4 ~
IADD.X_R_P_R_R_P
R_P_R_R_P
INT_ARITH
4 ~
IADD.X_R_P_R_R_R
R_P_R_R_R
INT_ARITH
4 ~
IADD.X_R_P_R_UR_P
R_P_R_UR_P
INT_ARITH
4 ~
IADD.X_R_R_II_P
R_R_II_P
INT_ARITH
4 ~
IADD.X_R_R_R_P
R_R_R_P
INT_ARITH
4 ~
IADD.X_R_R_UR_P
R_R_UR_P
INT_ARITH
4 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
IADD.X_R_P_R_R_P_?
R_P_R_R_P_?
INT_ARITH
4 ~
IADD.X_R_P_R_R_P_? — 9 fields · 1 samples
and_base: 0x0000000000000400000000001b000235
var_mask: 0x1c00000007800100800000ff00fff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[122]
1
t2
neg
[90]
1
t4
neg
[89:87]
3
t4
pred
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD.X_R_P_R_II_P — 5 fields · 32 samples
and_base: 0x0000000000000400fffffffe01007835
var_mask: 0x00000000038e000000000001fe7f0000
Bits
W
Tok
Extraction
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[32]
1
t4
imm
[31:25]
7
t3
imm
[22:16]
7
t1
reg
IADD.X_R_P_R_R_P — 5 fields · 32 samples
and_base: 0x00000000000004000000004000407235
var_mask: 0x00000000008200000000003fff3f0000
Bits
W
Tok
Extraction
[87]
1
t5
pred
[81]
1
t2
pred
[37:32]
6
t4
reg
[31:24]
8
t3
reg
[21:16]
6
t1
reg
IADD.X_R_P_R_R_R — 3 fields · 32 samples
and_base: 0x00000000010405000000000000007235
var_mask: 0x00000000000000000000003f7f7f0000
Bits
W
Tok
Extraction
[37:32]
6
t4
reg
[30:24]
7
t3
reg
[22:16]
7
t1
reg
IADD.X_R_P_R_UR_P — 5 fields · 32 samples
and_base: 0x00000000080004000000000000007c35
var_mask: 0x00000000038e00000000000f3f3f0000
Bits
W
Tok
Extraction
[89:87]
3
t5
pred
[83:81]
3
t2
pred
[35:32]
4
t4
ureg
[29:24]
6
t3
reg
[21:16]
6
t1
reg
IADD.X_R_R_II_P — 3 fields · 32 samples
and_base: 0x00000000000e0400ffffffff00007835
var_mask: 0x000000000380000000000000ff7f0000
Bits
W
Tok
Extraction
[89:87]
3
t4
pred
[31:24]
8
t2
imm
[22:16]
7
t1
reg
IADD.X_R_R_R_P — 9 fields
and_base: 0xe000000000000ff000235
var_mask: 0x1c00000007800100800000ff00fff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[122]
1
t2
neg
[90]
1
t4
neg
[89:87]
3
t4
pred
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD.X_R_R_UR_P — 4 fields · 13 samples
and_base: 0x00000000080e04000000000100007c35
var_mask: 0x00000000038000000000000e3f3f0000
Bits
W
Tok
Extraction
[89:87]
3
t4
pred
[35:33]
3
t3
ureg
[29:24]
6
t2
reg
[21:16]
6
t1
reg
IADD3
3-input integer add. Rd = Ra + Rb + Rc. Carry-out to Pd0/Pd1. The .X modifier reads carry-in from a predicate, enabling 64-bit addition via IADD3 (lo) + IADD3.X (hi).
InsKey
Operands
Modifiers
Pipeline
Latency
IADD3_P_R_P_P_R_II_R
P_R_P_P_R_II_R
—
INT_ARITH
4 ★
IADD3_P_R_P_P_R_R_R
P_R_P_P_R_R_R
—
INT_ARITH
4 ★
IADD3_P_R_P_P_R_UR_R
P_R_P_P_R_UR_R
—
INT_ARITH
4 ★
IADD3_R_P_P_R_II_II
R_P_P_R_II_II
—
INT_ARITH
4 ★
IADD3_R_P_P_R_II_R
R_P_P_R_II_R
X
INT_ARITH
4 ★
IADD3_R_P_P_R_II_R_P_P
R_P_P_R_II_R_P_P
X
INT_ARITH
4 ★
IADD3_R_P_P_R_R_II
R_P_P_R_R_II
—
INT_ARITH
4 ★
IADD3_R_P_P_R_R_II_II
R_P_P_R_R_II_II
—
INT_ARITH
4 ★
IADD3_R_P_P_R_R_R
R_P_P_R_R_R
X
INT_ARITH
4 ★
IADD3_R_P_P_R_R_R_P_P
R_P_P_R_R_R_P_P
X
INT_ARITH
4 ★
IADD3_R_P_P_R_UR_II
R_P_P_R_UR_II
—
INT_ARITH
4 ★
IADD3_R_P_P_R_UR_II_II
R_P_P_R_UR_II_II
—
INT_ARITH
4 ★
IADD3_R_P_P_R_UR_R
R_P_P_R_UR_R
X
INT_ARITH
4 ★
IADD3_R_P_P_R_UR_R_P_P
R_P_P_R_UR_R_P_P
X
INT_ARITH
4 ★
IADD3_R_P_P_R_UR_UR
R_P_P_R_UR_UR
—
INT_ARITH
4 ★
17 partial encodings — operand types not fully identified
3-input integer add. Rd = Ra + Rb + Rc. Carry-out to Pd0/Pd1. The .X modifier reads carry-in from a predicate, enabling 64-bit addition via IADD3 (lo) + IADD3.X (hi).
InsKey
Operands
Pipeline
Latency
IADD3.X_R_P_P_R_II_R_P_P
R_P_P_R_II_R_P_P
INT_ARITH
4 ★
IADD3.X_R_P_P_R_R_R_P_P
R_P_P_R_R_R_P_P
INT_ARITH
4 ★
IADD3.X_R_P_P_R_UR_R_P_P
R_P_P_R_UR_R_P_P
INT_ARITH
4 ★
IADD3.X_R_P_P_R_II_R_P_P — 4 fields · 32 samples
and_base: 0x000000000071e4ff0000000100007810
var_mask: 0x0000000001860000000000007f7f0000
Bits
W
Tok
Extraction
[88:87]
2
t7
pred
[82:81]
2
t2
pred
[30:24]
7
t4
reg
[22:16]
7
t1
reg
IADD3.X_R_P_P_R_R_R_P_P — 16 fields
and_base: 0xff00000000ff000210
var_mask: 0x1c00000007ffe900800000ff00fff000
Bits
W
Tok
Extraction
[124]
1
t6
neg
[123]
1
t5
neg
[123]
1
t5
reuse
[122]
1
t4
neg
[90]
1
t7
neg
[89:87]
3
t7
pred
[86:84]
3
t3
pred
[83:81]
3
t2
pred
[80]
1
t8
neg
[79:77]
3
t8
pred
[75]
1
t6
neg
[72]
1
t4
neg
[63]
1
t5
neg
[39:32]
8
t5
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IADD3.X_R_P_P_R_UR_R_P_P — 5 fields · 32 samples
and_base: 0x000000000871e4ff0000000000007c10
var_mask: 0x00000000018e00000000000f7f3f0000
Bits
W
Tok
Extraction
[88:87]
2
t7
pred
[83:81]
3
t2
pred
[35:32]
4
t5
ureg
[30:24]
7
t4
reg
[21:16]
6
t1
reg
IDP.2A.LO.U16.U8
Integer dot product. IDP.4A: 4-element dot product accumulate. Rd = Ra[3:0]⋅Rb[3:0] + Rc. Each element is 8-bit (S8 or U8). Equivalent to dp4a / __dp4a() in CUDA.
InsKey
Operands
Pipeline
Latency
IDP.2A.LO.U16.U8_R_R_R_R
R_R_R_R
INT_ARITH
4 ~
IDP.2A.LO.U16.U8_R_R_R_R — 7 fields
and_base: 0xff0000000000000226
var_mask: 0x1c00000000000800000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[75]
1
t4
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IDP.4A.S8.S8
Integer dot product. IDP.4A: 4-element dot product accumulate. Rd = Ra[3:0]⋅Rb[3:0] + Rc. Each element is 8-bit (S8 or U8). Equivalent to dp4a / __dp4a() in CUDA.
InsKey
Operands
Pipeline
Latency
IDP.4A.S8.S8_R_R_R_R
R_R_R_R
INT_ARITH
4 ~
IDP.4A.S8.S8_R_R_UR_UR
R_R_UR_UR
INT_ARITH
4 ~
2 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
IDP.4A.S8.S8_R_R_R_R_?
R_R_R_R_?
INT_ARITH
4 ~
IDP.4A.S8.S8_R_R_R_R_II_?
R_R_R_R_II_?
INT_ARITH
4 ~
IDP.4A.S8.S8_R_R_R_R_? — 2 fields · 2 samples
and_base: 0x000000000000062c0000003030417226
var_mask: 0x00000000000000000000000c08000000
Bits
W
Tok
Extraction
[35:34]
2
t3
reg
[27]
1
t2
reg
IDP.4A.S8.S8_R_R_R_R_II_? — 11 fields · 1 samples
and_base: 0x00000000000006000000000000000226
var_mask: 0xfc000000000000ff000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
neg
[124]
1
t4
reuse
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IDP.4A.S8.S8_R_R_R_R — 11 fields
and_base: 0x6000000000000000226
var_mask: 0xfc000000000000ff000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
neg
[124]
1
t4
reuse
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IDP.4A.S8.S8_R_R_UR_UR — 3 fields · 32 samples
and_base: 0x00000000080006ff0000000040007c26
var_mask: 0x00000000000000000000000f3f7f0000
Bits
W
Tok
Extraction
[35:32]
4
t3
ureg
[29:24]
6
t2
reg
[22:16]
7
t1
reg
IDP.4A.S8.U8
Integer dot product. IDP.4A: 4-element dot product accumulate. Rd = Ra[3:0]⋅Rb[3:0] + Rc. Each element is 8-bit (S8 or U8). Equivalent to dp4a / __dp4a() in CUDA.
InsKey
Operands
Pipeline
Latency
IDP.4A.S8.U8_R_R_R_R
R_R_R_R
INT_ARITH
4 ~
IDP.4A.S8.U8_R_R_R_R — 11 fields
and_base: 0xff0000000000000226
var_mask: 0x1c00200000000800000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
neg
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[109]
1
t2
neg
[75]
1
t4
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IDP.4A.U8.S8
Integer dot product. IDP.4A: 4-element dot product accumulate. Rd = Ra[3:0]⋅Rb[3:0] + Rc. Each element is 8-bit (S8 or U8). Equivalent to dp4a / __dp4a() in CUDA.
InsKey
Operands
Pipeline
Latency
IDP.4A.U8.S8_R_R_R_R
R_R_R_R
INT_ARITH
4 ~
IDP.4A.U8.S8_R_R_R_R — 7 fields
and_base: 0xff0000000000000226
var_mask: 0x1c00000000000800000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[75]
1
t4
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IDP.4A.U8.U8
Integer dot product. IDP.4A: 4-element dot product accumulate. Rd = Ra[3:0]⋅Rb[3:0] + Rc. Each element is 8-bit (S8 or U8). Equivalent to dp4a / __dp4a() in CUDA.
InsKey
Operands
Pipeline
Latency
IDP.4A.U8.U8_R_R_R_R
R_R_R_R
INT_ARITH
4 ~
IDP.4A.U8.U8_R_R_UR_R
R_R_UR_R
INT_ARITH
4 ~
IDP.4A.U8.U8_R_R_R_R — 11 fields
and_base: 0x226
var_mask: 0xfc000000000000ff000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
neg
[124]
1
t4
reuse
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IDP.4A.U8.U8_R_R_UR_R — 7 fields
and_base: 0x80000ff0000000000000c26
var_mask: 0x1c00000000000800000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[75]
1
t4
neg
[39:32]
8
t3
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IMAD
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
InsKey
Operands
Modifiers
Pipeline
Latency
IMAD_P0_R_R_II_R
P0_R_R_II_R
—
INT_ARITH
4 ★
IMAD_R_P_R_R_R
R_P_R_R_R
HI,U32, U32,WIDE, U32,WIDE,X, SHL,U32, U32, WIDE, X
INT_ARITH
4 ★
IMAD_R_P_R_R_R_P
R_P_R_R_R_P
U32,WIDE,X, HI,U32, U32,WIDE, SHL,U32, U32, WIDE, X
INT_ARITH
4 ★
IMAD_R_P_R_UR_R
R_P_R_UR_R
HI,U32, U32,WIDE, U32,WIDE,X, SHL,U32, U32, WIDE, X
INT_ARITH
4 ★
IMAD_R_P_R_UR_R_P
R_P_R_UR_R_P
U32,WIDE,X, HI,U32, U32,WIDE, SHL,U32, U32, WIDE, X
INT_ARITH
4 ★
IMAD_R_R_II_II_II
R_R_II_II_II
—
INT_ARITH
4 ★
IMAD_R_R_II_R
R_R_II_R
HI,U32, SHL,U32, U32, U32,WIDE, WIDE, U32,WIDE,X, X
INT_ARITH
4 ★
IMAD_R_R_II_R_R
R_R_II_R_R
—
INT_ARITH
4 ★
IMAD_R_R_R_II
R_R_R_II
HI,U32, U32,WIDE, U32,WIDE,X, SHL,U32, U32, WIDE, X
INT_ARITH
4 ★
IMAD_R_R_R_II_II_P
R_R_R_II_II_P
—
INT_ARITH
4 ★
IMAD_R_R_R_II_R
R_R_R_II_R
—
INT_ARITH
4 ★
IMAD_R_R_R_R
R_R_R_R
HI,U32, U32,WIDE, U32,WIDE,X, SHL,U32, U32, WIDE, X
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
InsKey
Operands
Pipeline
Latency
IMAD.HI_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
IMAD.HI_R_R_R_R — 10 fields
and_base: 0x78e00ff0000000000000225
var_mask: 0x1c00000000000800000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
neg
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[75]
1
t4
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IMAD.HI.U32
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
InsKey
Operands
Pipeline
Latency
IMAD.HI.U32_R_P_R_R_R
R_P_R_R_R
INT_ARITH
6 ★
IMAD.HI.U32_R_P_R_UR_R
R_P_R_UR_R
INT_ARITH
6 ★
IMAD.HI.U32_R_R_II_II
R_R_II_II
INT_ARITH
6 ★
IMAD.HI.U32_R_R_R_R
R_R_R_R
INT_ARITH
6 ★
IMAD.HI.U32_R_R_UR_UR
R_R_UR_UR
INT_ARITH
6 ★
IMAD.HI.U32_R_P_R_R_R — 5 fields · 32 samples
and_base: 0x00000000078000000000000000017227
var_mask: 0x00000000000e003e0000007f3f3e0000
Bits
W
Tok
Extraction
[83:81]
3
t2
pred
[69:65]
5
t5
reg
[38:32]
7
t4
reg
[29:24]
6
t3
reg
[21:17]
5
t1
reg
IMAD.HI.U32_R_P_R_UR_R — 5 fields · 32 samples
and_base: 0x000000000f8000000000000000007c27
var_mask: 0x00000000000e003e0000001c3f3f0000
Bits
W
Tok
Extraction
[83:81]
3
t2
pred
[69:65]
5
t5
reg
[36:34]
3
t4
ureg
[29:24]
6
t3
reg
[21:16]
6
t1
reg
IMAD.HI.U32_R_R_II_II — 3 fields · 32 samples
and_base: 0x00000000078e00ff0000000000007827
var_mask: 0x00000000000000007fffffff7f7f0000
Bits
W
Tok
Extraction
[62:32]
31
t3
imm
[30:24]
7
t2
reg
[22:16]
7
t1
reg
IMAD.HI.U32_R_R_R_R — 12 fields
and_base: 0x78e00000000000000000225
var_mask: 0x1c000000000008ff000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
neg
[124]
1
t4
reuse
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[75]
1
t4
neg
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IMAD.HI.U32_R_R_UR_UR — 3 fields · 32 samples
and_base: 0x000000000f8e00ff0000000501017c27
var_mask: 0x0000000000000000000000027e7e0000
Bits
W
Tok
Extraction
[33]
1
t3
ureg
[30:25]
6
t2
reg
[22:17]
6
t1
reg
IMAD.IADD.U32
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
InsKey
Operands
Pipeline
Latency
IMAD.IADD.U32_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
IMAD.IADD.U32_R_R_II_R — 4 fields · 6 samples
and_base: 0x00000000078e00000000000100000824
var_mask: 0x000000000000001f000000007f7f3000
Bits
W
Tok
Extraction
[68:64]
5
t4
reg
[30:24]
7
t2
reg
[22:16]
7
t1
reg
[13:12]
2
t0
guard
IMAD.SHL.U32
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
InsKey
Operands
Pipeline
Latency
IMAD.SHL.U32_P_R_R_II_R
P_R_R_II_R
INT_ARITH
4 ★
IMAD.SHL.U32_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
3 partial encodings — operand types not fully identified
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
InsKey
Operands
Pipeline
Latency
IMAD.U32_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
4 partial encodings — operand types not fully identified
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
InsKey
Operands
Pipeline
Latency
IMAD.WIDE_R_R_II_R
R_R_II_R
INT_ARITH
6 ★
IMAD.WIDE_R_R_II_R_R
R_R_II_R_R
INT_ARITH
6 ★
IMAD.WIDE_R_R_R_R
R_R_R_R
INT_ARITH
6 ★
IMAD.WIDE_R_R_R_R_R
R_R_R_R_R
INT_ARITH
6 ★
IMAD.WIDE_R_R_R_UR
R_R_R_UR
INT_ARITH
6 ★
IMAD.WIDE_R_R_UR_R
R_R_UR_R
INT_ARITH
6 ★
IMAD.WIDE_R_R_UR_R_R
R_R_UR_R_R
INT_ARITH
6 ★
2 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
IMAD.WIDE_R_R_II_R_II_?
R_R_II_R_II_?
INT_ARITH
6 ★
IMAD.WIDE_R_R_UR_R_II_?
R_R_UR_R_II_?
INT_ARITH
6 ★
IMAD.WIDE_R_R_UR_R_II_? — 1 fields · 18 samples
and_base: 0x000000000f8e023400000004330e7c25
var_mask: 0x00000000000000020000000000000000
Bits
W
Tok
Extraction
[65]
1
t4
reg
IMAD.WIDE_R_R_II_R — 8 fields
and_base: 0x78e00000000000000000824
var_mask: 0x1c000000000008fffffffffffffff000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[122]
1
t2
reuse
[75]
1
t4
neg
[71:64]
8
t4
reg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IMAD.WIDE_R_R_II_R_R — 4 fields · 10 samples
and_base: 0x00000000078e02200000000001007825
var_mask: 0x000000000000001e000000067e1c0000
Bits
W
Tok
Extraction
[68:65]
4
t4
reg
[34:33]
2
t3
imm
[30:25]
6
t2
reg
[20:18]
3
t1
reg
IMAD.WIDE_R_R_R_R — 7 fields
and_base: 0x78e00ff0000000000000224
var_mask: 0x1c00000000000800000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[75]
1
t4
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
IMAD.WIDE_R_R_R_R_R — 4 fields · 32 samples
and_base: 0x00000000078e02000000000000007225
var_mask: 0x000000000800001f000000060f0e0c00
Bits
W
Tok
Extraction
[68:64]
5
t4
reg
[34:33]
2
t3
reg
[27:24]
4
t2
reg
[19:17]
3
t1
reg
IMAD.WIDE_R_R_R_UR — 5 fields · 32 samples
and_base: 0x00000000078e02000000000000000225
var_mask: 0x00000000080000ff0000003ffffefc00
Bits
W
Tok
Extraction
[71:64]
8
t3
reg
[37:32]
6
t4
ureg
[31:24]
8
t2
reg
[23:17]
7
t1
reg
[15:12]
4
t0
guard
IMAD.WIDE_R_R_UR_R — 5 fields · 32 samples
and_base: 0x000000000f8e02000000000000000c25
var_mask: 0x00000000000000ff0000001f7f7ef000
Bits
W
Tok
Extraction
[71:64]
8
t4
reg
[36:32]
5
t3
ureg
[30:24]
7
t2
reg
[22:17]
6
t1
reg
[15:12]
4
t0
guard
IMAD.WIDE_R_R_UR_R_R — 4 fields · 27 samples
and_base: 0x000000000f8e02000000000000007c25
var_mask: 0x000000000000003e0000001f3f1e0000
Bits
W
Tok
Extraction
[69:65]
5
t4
reg
[36:32]
5
t3
ureg
[29:24]
6
t2
reg
[20:17]
4
t1
reg
IMAD.WIDE.U32
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
InsKey
Operands
Pipeline
Latency
IMAD.WIDE.U32_R_P_R_R_R
R_P_R_R_R
INT_ARITH
6 ★
IMAD.WIDE.U32_R_P_R_UR_R
R_P_R_UR_R
INT_ARITH
6 ★
IMAD.WIDE.U32_R_R_II_II
R_R_II_II
INT_ARITH
6 ★
IMAD.WIDE.U32_R_R_II_R
R_R_II_R
INT_ARITH
6 ★
IMAD.WIDE.U32_R_R_II_R_R
R_R_II_R_R
INT_ARITH
6 ★
IMAD.WIDE.U32_R_R_R_II_II
R_R_R_II_II
INT_ARITH
6 ★
IMAD.WIDE.U32_R_R_R_R
R_R_R_R
INT_ARITH
6 ★
IMAD.WIDE.U32_R_R_UR_II_II
R_R_UR_II_II
INT_ARITH
6 ★
IMAD.WIDE.U32_R_R_UR_R
R_R_UR_R
INT_ARITH
6 ★
8 partial encodings — operand types not fully identified
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
Integer multiply-add. Rd = Ra × Rb + Rc. The most common multiply instruction on SM120. .WIDE: 64-bit result in register pair (Ra×Rb is 32×32→64). .HI: upper 32 bits of Ra×Rb. .IADD.U32: fused IMAD+IADD form emitted by ptxas. .U32 suffix: unsigned multiply (default is signed).
Generic load (address space determined by pointer).
InsKey
Operands
Pipeline
Latency
LD.E.64_R_dARI
R_dARI
MEMORY
200 ~
LD.E.64_R_dARI_II
R_dARI_II
MEMORY
200 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LD.E.64_R_dARI_II_?
R_dARI_II_?
MEMORY
200 ~
LD.E.64_R_dARI_II_? — 4 fields · 9 samples
and_base: 0x000000000c101b000000000800007980
var_mask: 0x00000000000000000001f8067e3e0000
Bits
W
Tok
Extraction
[48:43]
6
t2
imm
[34:33]
2
t2
ureg
[30:25]
6
t2
reg
[21:17]
5
t1
reg
LD.E.64_R_dARI — 4 fields · 32 samples
and_base: 0x000000000c101b000000000000007980
var_mask: 0x00000000000000000000781e3e3e0000
Bits
W
Tok
Extraction
[46:43]
4
t2
imm
[36:33]
4
t2
ureg
[29:25]
5
t2
reg
[21:17]
5
t1
reg
LD.E.64_R_dARI_II — 5 fields · 27 samples
and_base: 0x000000000c101b000000000000001980
var_mask: 0x00000000000000000003f81e7e7ee000
Bits
W
Tok
Extraction
[49:43]
7
t2
imm
[36:33]
4
t2
ureg
[30:25]
6
t2
reg
[22:17]
6
t1
reg
[15:13]
3
t0
guard
LD.E.S8
Generic load (address space determined by pointer).
InsKey
Operands
Pipeline
Latency
LD.E.S8_R_dARI
R_dARI
MEMORY
200 ~
LD.E.S8_R_dARI — 3 fields · 32 samples
and_base: 0x000000000c1013000000000000007980
var_mask: 0x00000000000000000000000e3e3e0000
Bits
W
Tok
Extraction
[35:33]
3
t2
ureg
[29:25]
5
t2
reg
[21:17]
5
t1
reg
LD.E.U16
Generic load (address space determined by pointer).
InsKey
Operands
Pipeline
Latency
LD.E.U16_R_dARI
R_dARI
MEMORY
200 ~
LD.E.U16_R_dARI_II
R_dARI_II
MEMORY
200 ~
3 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LD.E.U16_R_dARI_II_?
R_dARI_II_?
MEMORY
200 ~
LD.E.U16_R_dARI_II_II_?
R_dARI_II_II_?
MEMORY
200 ~
LD.E.U16_R_dARI_II_II_II_?
R_dARI_II_II_II_?
MEMORY
200 ~
LD.E.U16_R_dARI_II_? — 3 fields · 5 samples
and_base: 0x000000000c1015000000000000007980
var_mask: 0x00000000000000000000003c1e1e0000
Bits
W
Tok
Extraction
[37:34]
4
t2
ureg
[28:25]
4
t2
reg
[20:17]
4
t1
reg
LD.E.U16_R_dARI_II_II_? — 3 fields · 3 samples
and_base: 0x000000000c1015000000000008037980
var_mask: 0x00000000000000000000003c02080000
Bits
W
Tok
Extraction
[37:34]
4
t2
ureg
[25]
1
t2
reg
[19]
1
t1
reg
LD.E.U16_R_dARI_II_II_II_? — 3 fields · 6 samples
and_base: 0x000000000c1015000000000800107980
var_mask: 0x0000000000000000000000061e0e0000
Bits
W
Tok
Extraction
[34:33]
2
t2
ureg
[28:25]
4
t2
reg
[19:17]
3
t1
reg
LD.E.U16_R_dARI — 4 fields · 32 samples
and_base: 0x000000000c1015000000000800000980
var_mask: 0x000000000000000000000004fe7ff000
Bits
W
Tok
Extraction
[34]
1
t2
ureg
[31:25]
7
t2
reg
[22:16]
7
t1
reg
[15:12]
4
t0
guard
LD.E.U16_R_dARI_II — 5 fields · 26 samples
and_base: 0x000000000c1015000000000000000980
var_mask: 0x00000000000000000000803e3e3ff000
Bits
W
Tok
Extraction
[47]
1
t2
imm
[37:33]
5
t2
ureg
[29:25]
5
t2
reg
[21:16]
6
t1
reg
[15:12]
4
t0
guard
LD.E.U8
Generic load (address space determined by pointer).
InsKey
Operands
Pipeline
Latency
LD.E.U8_R_dARI
R_dARI
MEMORY
200 ~
LD.E.U8_R_dARI — 4 fields · 32 samples
and_base: 0x000000000c1011000000000000008980
var_mask: 0x00000000000000000000001e7e7f3000
Bits
W
Tok
Extraction
[36:33]
4
t2
ureg
[30:25]
6
t2
reg
[22:16]
7
t1
reg
[13:12]
2
t0
guard
LDC
Load from constant memory. c[bank][offset] addressing. Bank 0 offset 0x160+ holds kernel launch arguments. ~5 cycle latency when data is in the constant cache (broadcast).
InsKey
Operands
Modifiers
Pipeline
Latency
LDC_R_II
R_II
—
SPECIAL
5 ~
LDC_R_cAI
R_cAI
64
SPECIAL
5 ~
LDC_R_cAI_II
R_cAI_II
—
SPECIAL
5 ~
LDC_R_cARI
R_cARI
64
SPECIAL
5 ~
3 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDC_R_cAI_II_?
R_cAI_II_?
SPECIAL
5 ~
LDC_R_cAI_II_II_?
R_cAI_II_II_?
SPECIAL
5 ~
LDC_R_cAI_II_II_II_?
R_cAI_II_II_II_?
SPECIAL
5 ~
LDC_R_cAI_II_? — 3 fields · 32 samples
and_base: 0x00000000000008000000c000ff004b82
var_mask: 0x000000000000000000003f00003f3000
Bits
W
Tok
Extraction
[45:40]
6
t2
imm
[21:16]
6
t1
reg
[13:12]
2
t0
guard
LDC_R_cAI_II_II_? — 3 fields · 32 samples
and_base: 0x00000000000008000000c000ff000b82
var_mask: 0x000000000000000000003f00003f7000
Bits
W
Tok
Extraction
[45:40]
6
t2
imm
[21:16]
6
t1
reg
[14:12]
3
t0
guard
LDC_R_cAI_II_II_II_? — 2 fields · 32 samples
and_base: 0x00000000000008000000c000ff007b82
var_mask: 0x000000000000000000003f00001f0000
Bits
W
Tok
Extraction
[45:40]
6
t2
imm
[20:16]
5
t1
reg
LDC_R_II — 3 fields
and_base: 0xff000b82
var_mask: 0x1c0000000000000007ffffc000fff000
Bits
W
Tok
Extraction
[58:38]
21
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDC_R_cAI — 2 fields · 84 samples
and_base: 0x00000000000008000000c000ff007b82
var_mask: 0x1c0000000000000000003f0000ff0000
Bits
W
Tok
Extraction
[58:38]
21
t2
sub_imm1
[23:16]
8
t1
reg
LDC_R_cAI.64 — 5 fields
and_base: 0x0000000000000a000000000000000b82
var_mask: 0x1ffffe000000000007ffffc0fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[58:38]
21
t2
cm16_off
[31:24]
8
t2
sub_r1
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDC_R_cAI_II — 2 fields · 32 samples
and_base: 0x000000000000080000000000ff007b82
var_mask: 0x00000000000000000001ff0000ff0000
Bits
W
Tok
Extraction
[48:40]
9
t2
imm
[23:16]
8
t1
reg
LDC_R_cARI — 4 fields · 167 samples
and_base: 0x00000000000008000080000000007b82
var_mask: 0x1c0000000000000000607f00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[58:38]
21
t2
cm16_off
[31:24]
8
t2
sub_r1
[23:16]
8
t1
reg
LDC_R_cARI.64 — 5 fields · 5 samples
and_base: 0x0000000000000a0000c0000000000b82
var_mask: 0x1c0000000000000000000600fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[58:38]
21
t2
cm16_off
[31:24]
8
t2
sub_r1
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDC.64
Load from constant memory. c[bank][offset] addressing. Bank 0 offset 0x160+ holds kernel launch arguments. ~5 cycle latency when data is in the constant cache (broadcast).
InsKey
Operands
Pipeline
Latency
LDC.64_P_R_cAI
P_R_cAI
SPECIAL
5 ~
LDC.64_R_II
R_II
SPECIAL
5 ~
LDC.64_R_cAI
R_cAI
SPECIAL
5 ~
LDC.64_R_cAI_II
R_cAI_II
SPECIAL
5 ~
4 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDC.64_R_cAI_II_?
R_cAI_II_?
SPECIAL
5 ~
LDC.64_R_cAI_II_II_?
R_cAI_II_II_?
SPECIAL
5 ~
LDC.64_R_cAI_II_II_II_?
R_cAI_II_II_II_?
SPECIAL
5 ~
LDC.64_R_cAI_II_II_II_II_?
R_cAI_II_II_II_II_?
SPECIAL
5 ~
LDC.64_R_cAI_II_? — 3 fields · 32 samples
and_base: 0x0000000000000a0000000000ff000b82
var_mask: 0x00000000000000000001fe00001ef000
Bits
W
Tok
Extraction
[48:41]
8
t2
imm
[20:17]
4
t1
reg
[15:12]
4
t0
guard
LDC.64_R_cAI_II_II_? — 3 fields · 32 samples
and_base: 0x0000000000000a0000000000ff000b82
var_mask: 0x00000000000000000001fe00001e7000
Bits
W
Tok
Extraction
[48:41]
8
t2
imm
[20:17]
4
t1
reg
[14:12]
3
t0
guard
LDC.64_P_R_cAI — 3 fields
and_base: 0xff000b82
var_mask: 0x1c0000000000000007ffffc000fff000
Bits
W
Tok
Extraction
[58:38]
21
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDC.64_R_II — 3 fields
and_base: 0xff000b82
var_mask: 0x1c0000000000000007ffffc000fff000
Bits
W
Tok
Extraction
[58:38]
21
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDC.64_R_cAI — 3 fields
and_base: 0xff000b82
var_mask: 0x1c0000000000000007ffffc000fff000
Bits
W
Tok
Extraction
[58:38]
21
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDC.64_R_cAI_II — 3 fields · 32 samples
and_base: 0x0000000000000a0000000000ff000b82
var_mask: 0x00000000000000000001fe0000fe7000
Bits
W
Tok
Extraction
[48:41]
8
t2
imm
[23:17]
7
t1
reg
[14:12]
3
t0
guard
LDC.U16
Load from constant memory. c[bank][offset] addressing. Bank 0 offset 0x160+ holds kernel launch arguments. ~5 cycle latency when data is in the constant cache (broadcast).
InsKey
Operands
Pipeline
Latency
LDC.U16_R_cAI
R_cAI
SPECIAL
5 ~
LDC.U16_R_cAI_II
R_cAI_II
SPECIAL
5 ~
LDC.U16_R_cAI — 3 fields · 32 samples
and_base: 0x00000000000004000000f400ff008b82
var_mask: 0x000000000000000000000080003f1000
Bits
W
Tok
Extraction
[39]
1
t2
imm
[21:16]
6
t1
reg
[12]
1
t0
guard
LDC.U16_R_cAI_II — 3 fields · 1 samples
and_base: 0x00000000000004000000fc00ff006b82
var_mask: 0x000000000000000000000080003f1000
Bits
W
Tok
Extraction
[39]
1
t2
imm
[21:16]
6
t1
reg
[12]
1
t0
guard
LDC.U8
Load from constant memory. c[bank][offset] addressing. Bank 0 offset 0x160+ holds kernel launch arguments. ~5 cycle latency when data is in the constant cache (broadcast).
InsKey
Operands
Pipeline
Latency
LDC.U8_R_cAI
R_cAI
SPECIAL
5 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDC.U8_R_cAI_?
R_cAI_?
SPECIAL
5 ~
LDC.U8_R_cAI_? — 1 fields · 32 samples
and_base: 0x000000000000000000016240ff007b82
var_mask: 0x00000000000000000000000000fe0000
Bits
W
Tok
Extraction
[23:17]
7
t1
reg
LDC.U8_R_cAI — 2 fields · 32 samples
and_base: 0x000000000000000000016000ff007b82
var_mask: 0x000000000000000000001fc000ff0000
Bits
W
Tok
Extraction
[44:38]
7
t2
imm
[23:16]
8
t1
reg
LDCU
Uniform constant memory load — result written to a uniform register UR.
InsKey
Operands
Modifiers
Pipeline
Latency
LDCU_P_UR_II
P_UR_II
—
SPECIAL
5 ~
LDCU_UR_cAI
UR_cAI
128, 64, U8
SPECIAL
5 ~
LDCU_UR_cARI
UR_cARI
64, 128, U8
SPECIAL
5 ~
LDCU_UR_cAURI
UR_cAURI
128, 64, U8
SPECIAL
5 ~
LDCU_P_UR_II — 3 fields
and_base: 0x800000000000000ff0001ac
var_mask: 0x1c0000000000000007ffffe000fff000
Bits
W
Tok
Extraction
[58:37]
22
t2
imm
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
LDCU_UR_cAI — 2 fields · 32 samples
and_base: 0x000000000800080000004000ff0077ac
var_mask: 0x1c0000000000000000003f8000ff0000
Bits
W
Tok
Extraction
[58:37]
22
t2
sub_imm1
[23:16]
8
t1
ureg
LDCU_UR_cAI.128 — 2 fields · 2 samples
and_base: 0x0000000008000c0000c00000ff0077ac
var_mask: 0x1c000000000000000000020000ff0000
Bits
W
Tok
Extraction
[58:37]
22
t2
cm17_off
[23:16]
8
t1
ureg
LDCU_UR_cAI.64 — 2 fields · 52 samples
and_base: 0x0000000008000a0000000000ff0077ac
var_mask: 0x1c000000000000000100ff0000ff0000
Bits
W
Tok
Extraction
[58:37]
22
t2
cm17_off
[23:16]
8
t1
ureg
LDCU_UR_cAI.U8 — 4 fields
and_base: 0x000000000800000000000000000077ac
var_mask: 0x1ffffe000000000007ffffe0ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[58:37]
22
t2
cm17_off
[31:24]
8
t2
sub_r1
[23:16]
8
t1
ureg
LDCU_UR_cARI.64 — 2 fields · 60 samples
and_base: 0x8000a0000000000ff0077ac
var_mask: 0x1c000000000000000000ff00001e0000
Bits
W
Tok
Extraction
[47:40]
8
t0
[20:17]
4
t0
LDCU_UR_cARI — 2 fields · 90 samples
and_base: 0x800080000006000ff0077ac
var_mask: 0x1c0000000000000000001f80001f0000
Bits
W
Tok
Extraction
[44:39]
6
t0
[20:16]
5
t1
ureg
LDCU_UR_cARI.128 — 2 fields · 2 samples
and_base: 0x0000000008000c0000c00000ff0077ac
var_mask: 0x1c000000000000000000020000ff0000
Bits
W
Tok
Extraction
[58:37]
22
t2
imm
[23:16]
8
t1
ureg
LDCU_UR_cARI.U8 — 2 fields · 1 samples
and_base: 0x000000000800000000000000ff0077ac
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[47:40]
8
t0
[20:17]
4
t0
LDCU_UR_cAURI — 4 fields · 63 samples
and_base: 0x000000000800080000c00000000077ac
var_mask: 0x1c0000000000000000000380ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[58:37]
22
t2
cm17_off
[31:24]
8
t2
sub_ur1
[23:16]
8
t1
ureg
LDCU_UR_cAURI.128 — 2 fields · 2 samples
and_base: 0x0000000008000c0000c00000ff0077ac
var_mask: 0x1c000000000000000000020000ff0000
Bits
W
Tok
Extraction
[58:37]
22
t2
cm17_off
[23:16]
8
t1
ureg
LDCU_UR_cAURI.64 — 2 fields · 52 samples
and_base: 0x0000000008000a0000000000ff0077ac
var_mask: 0x1c000000000000000100ff0000ff0000
Bits
W
Tok
Extraction
[58:37]
22
t2
cm17_off
[23:16]
8
t1
ureg
LDCU_UR_cAURI.U8 — 4 fields · 1 samples
and_base: 0x000000000800000000000000000077ac
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[58:37]
22
t2
cm17_off
[31:24]
8
t2
sub_ur1
[23:16]
8
t1
ureg
LDCU.128
Uniform constant memory load — result written to a uniform register UR.
InsKey
Operands
Pipeline
Latency
LDCU.128_UR_cAI
UR_cAI
SPECIAL
5 ~
LDCU.128_UR_cAI — 3 fields
and_base: 0x800000000000000ff0001ac
var_mask: 0x1c0000000000000007ffffe000fff000
Bits
W
Tok
Extraction
[58:37]
22
t2
imm
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
LDCU.64
Uniform constant memory load — result written to a uniform register UR.
InsKey
Operands
Pipeline
Latency
LDCU.64_UR_II
UR_II
SPECIAL
5 ~
LDCU.64_UR_cAI
UR_cAI
SPECIAL
5 ~
LDCU.64_UR_cAI_II
UR_cAI_II
SPECIAL
5 ~
2 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDCU.64_UR_cAI_II_?
UR_cAI_II_?
SPECIAL
5 ~
LDCU.64_UR_cAI_II_II_?
UR_cAI_II_II_?
SPECIAL
5 ~
LDCU.64_UR_cAI_II_? — 2 fields · 32 samples
and_base: 0x0000000008000a0000000000ff0077ac
var_mask: 0x00000000000000000000ff00003e0000
Bits
W
Tok
Extraction
[47:40]
8
t2
imm
[21:17]
5
t1
ureg
LDCU.64_UR_II — 3 fields
and_base: 0x800000000000000ff0001ac
var_mask: 0x1c0000000000000007ffffe000fff000
Bits
W
Tok
Extraction
[58:37]
22
t2
imm
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
LDCU.64_UR_cAI — 3 fields
and_base: 0x800000000000000ff0001ac
var_mask: 0x1c0000000000000007ffffe000fff000
Bits
W
Tok
Extraction
[58:37]
22
t2
imm
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
LDCU.64_UR_cAI_II — 2 fields · 32 samples
and_base: 0x0000000008000a0000000000ff0077ac
var_mask: 0x00000000000000000000ff00001e0000
Bits
W
Tok
Extraction
[47:40]
8
t2
imm
[20:17]
4
t1
ureg
LDCU.U16
Uniform constant memory load — result written to a uniform register UR.
InsKey
Operands
Pipeline
Latency
LDCU.U16_UR_cAI
UR_cAI
SPECIAL
5 ~
LDCU.U16_UR_cAI — 3 fields
and_base: 0x800000000000000ff0001ac
var_mask: 0x1c0000000000000007ffffe000fff000
Bits
W
Tok
Extraction
[58:37]
22
t2
imm
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
LDCU.U8
Uniform constant memory load — result written to a uniform register UR.
InsKey
Operands
Pipeline
Latency
LDCU.U8_UR_cAI
UR_cAI
SPECIAL
5 ~
LDCU.U8_UR_cAI — 2 fields · 32 samples
and_base: 0x000000000800000000008000ff0077ac
var_mask: 0x000000000000000000003fe0001f0000
Bits
W
Tok
Extraction
[45:37]
9
t2
imm
[20:16]
5
t1
ureg
LDG
Load from global memory via descriptor. Long latency (~200+ cycles), dispatched to LSU pipe, requires write barrier for result.
InsKey
Operands
Modifiers
Pipeline
Latency
LDG_R_ARI
R_ARI
E, 64,E, E,GPU,STRONG, 128,E,LTC128B, 128,E, CONSTANT,E, E,S8, E,U16, E,U8
MEMORY
200 ~
LDG_R_ARURI
R_ARURI
E, 64,E, E,GPU,STRONG, 128,E,LTC128B, 128,E, CONSTANT,E, E,S8, E,U16, E,U8
MEMORY
200 ~
LDG_R_dARI
R_dARI
128,E, 64,E, CONSTANT,E, E, E,S8, E,U16, E,U8, E,GPU,STRONG, 128,E,LTC128B
Load from global memory via descriptor. Long latency (~200+ cycles), dispatched to LSU pipe, requires write barrier for result.
InsKey
Operands
Pipeline
Latency
LDG.E.U8_R_dARI
R_dARI
MEMORY
200 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDG.E.U8_R_dARI_?
R_dARI_?
MEMORY
200 ~
LDG.E.U8_R_dARI — 4 fields · 32 samples
and_base: 0x000000000c1e11000000000000000981
var_mask: 0x00000000000000000000000e1e1ff000
Bits
W
Tok
Extraction
[35:33]
3
t2
ureg
[28:25]
4
t2
reg
[20:16]
5
t1
reg
[15:12]
4
t0
guard
LDG.E.U8.CONSTANT
Load from global memory via descriptor. Long latency (~200+ cycles), dispatched to LSU pipe, requires write barrier for result.
InsKey
Operands
Pipeline
Latency
LDG.E.U8.CONSTANT_R_dARI
R_dARI
MEMORY
200 ~
LDG.E.U8.CONSTANT_R_dARI — 4 fields · 32 samples
and_base: 0x000000000c1e91000000000000000981
var_mask: 0x00000000000000000000000e3e3ff000
Bits
W
Tok
Extraction
[35:33]
3
t2
ureg
[29:25]
5
t2
reg
[21:16]
6
t1
reg
[15:12]
4
t0
guard
LDGDEPBAR
Dependency barrier for asynchronous LDG operations. Waits for pending async LDGs.
InsKey
Operands
Pipeline
Latency
LDGDEPBAR
BARRIER
0 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDGDEPBAR_?
?
BARRIER
0 ~
LDGDEPBAR — 3 fields · 150 samples
and_base: 0x79af
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
[5]
1
t0
imm
[2]
1
t0
imm
LDGSTS
Asynchronous global→shared memory copy. Implements cp.async. The copy is issued to the async copy engine; completion is signaled via DEPBAR / LDGDEPBAR. Supports 4, 8, 16-byte transfers with optional zero-fill on predicated execution.
Asynchronous global→shared memory copy. Implements cp.async. The copy is issued to the async copy engine; completion is signaled via DEPBAR / LDGDEPBAR. Supports 4, 8, 16-byte transfers with optional zero-fill on predicated execution.
InsKey
Operands
Pipeline
Latency
LDGSTS.E_ARI_dARI
ARI_dARI
MEMORY
200 ~
LDGSTS.E_AR_dARI
AR_dARI
MEMORY
200 ~
LDGSTS.E_ARI_dARI — 4 fields · 32 samples
and_base: 0x000000000b9a10200000000060670fae
var_mask: 0x00000000000000000fffc1fc0c007000
Bits
W
Tok
Extraction
[59:46]
14
t1
imm
[40:34]
7
t2
imm
[27:26]
2
t2
reg
[14:12]
3
t0
guard
LDGSTS.E_AR_dARI — 8 fields
and_base: 0xb8810000000000000000fae
var_mask: 0x1c000000000000fffffffffffffff000
Bits
W
Tok
Extraction
[124]
1
t2
reuse
[122]
1
t2
reuse
[71:64]
8
t2
ureg
[63:44]
20
t1
imm
[43:32]
12
t2
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDGSTS.E.64
Asynchronous global→shared memory copy. Implements cp.async. The copy is issued to the async copy engine; completion is signaled via DEPBAR / LDGDEPBAR. Supports 4, 8, 16-byte transfers with optional zero-fill on predicated execution.
InsKey
Operands
Pipeline
Latency
LDGSTS.E.64_ARI_dARI
ARI_dARI
MEMORY
200 ~
LDGSTS.E.64_AR_dARI
AR_dARI
MEMORY
200 ~
LDGSTS.E.64_ARI_dARI — 6 fields · 32 samples
and_base: 0x000000000b9a141a0000000000000fae
var_mask: 0x000000000000000407ff81f87e7ff000
Bits
W
Tok
Extraction
[66]
1
t2
ureg
[58:47]
12
t1
imm
[40:35]
6
t2
imm
[30:25]
6
t2
reg
[22:16]
7
t1
reg
[15:12]
4
t0
guard
LDGSTS.E.64_AR_dARI — 5 fields · 32 samples
and_base: 0x000000000b9a14120000000000000fae
var_mask: 0x000000000000000c000001007e7ff000
Bits
W
Tok
Extraction
[67:66]
2
t2
ureg
[40]
1
t2
imm
[30:25]
6
t2
reg
[22:16]
7
t1
reg
[15:12]
4
t0
guard
LDGSTS.E.BYPASS.128
Asynchronous global→shared memory copy. Implements cp.async. The copy is issued to the async copy engine; completion is signaled via DEPBAR / LDGDEPBAR. Supports 4, 8, 16-byte transfers with optional zero-fill on predicated execution.
Asynchronous global→shared memory copy. Implements cp.async. The copy is issued to the async copy engine; completion is signaled via DEPBAR / LDGDEPBAR. Supports 4, 8, 16-byte transfers with optional zero-fill on predicated execution.
Asynchronous global→shared memory copy. Implements cp.async. The copy is issued to the async copy engine; completion is signaled via DEPBAR / LDGDEPBAR. Supports 4, 8, 16-byte transfers with optional zero-fill on predicated execution.
Asynchronous global→shared memory copy. Implements cp.async. The copy is issued to the async copy engine; completion is signaled via DEPBAR / LDGDEPBAR. Supports 4, 8, 16-byte transfers with optional zero-fill on predicated execution.
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDL_R_AR_?
R_AR_?
MEMORY_LOCAL
100 ~
LDL_R_AR_? — 1 fields · 4 samples
and_base: 0x00000000001008000000000001007983
var_mask: 0x000000000000000000000000003f0000
Bits
W
Tok
Extraction
[21:16]
6
t1
reg
LDL_R_AI.U8 — 5 fields · 15 samples
and_base: 0x000000000810000000001000ff027983
var_mask: 0x1c00000000000000ffffffff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[39:32]
8
t2
sub_ur0
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL_R_AI — 5 fields · 326 samples
and_base: 0x00000000001008000000000000000983
var_mask: 0x1c00000000000000ffffff00fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDL_R_AI.128 — 4 fields · 41 samples
and_base: 0x0000000000100c000000000000007983
var_mask: 0x1c00000000000000ffffff00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL_R_AI.64 — 4 fields · 225 samples
and_base: 0x0000000000100a000000000000007983
var_mask: 0x1c00000000000000ffffff00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL_R_AI.64,LU — 3 fields · 3 samples
and_base: 0x0000000000300a000000000001187983
var_mask: 0x1c00000000000000ffffff0000ff0000
Bits
W
Tok
Extraction
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL_R_AI.LU — 5 fields · 1 samples
and_base: 0x00000000003008000000000000007983
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[39:32]
8
t2
sub_ur0
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL_R_AI.S8 — 3 fields · 7 samples
and_base: 0x0000000000100200000000000a027983
var_mask: 0x1c00000000000000ffffff0000ff0000
Bits
W
Tok
Extraction
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL_R_AR — 5 fields
and_base: 0x983
var_mask: 0x1c00000000000000ffffff00fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDL_R_ARI — 5 fields · 326 samples
and_base: 0x00000000001008000000000000000983
var_mask: 0x1c00000000000000ffffff00fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDL_R_ARI.128 — 4 fields · 41 samples
and_base: 0x0000000000100c000000000000007983
var_mask: 0x1c00000000000000ffffff00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL_R_ARI.64 — 4 fields · 225 samples
and_base: 0x0000000000100a000000000000007983
var_mask: 0x1c00000000000000ffffff00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL_R_ARI.64,LU — 2 fields · 3 samples
and_base: 0x0000000000300a000000000001187983
var_mask: 0x1c00000000000000ffffff0000ff0000
Bits
W
Tok
Extraction
[63:40]
24
t2
sub_imm1
[23:16]
8
t1
reg
LDL_R_ARI.LU — 5 fields · 1 samples
and_base: 0x00000000003008000000000000000983
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDL_R_ARI.S8 — 2 fields · 7 samples
and_base: 0x0000000000100200000000000a027983
var_mask: 0x1c00000000000000ffffff0000ff0000
Bits
W
Tok
Extraction
[63:40]
24
t2
sub_imm1
[23:16]
8
t1
reg
LDL_R_ARI.U8 — 4 fields · 22 samples
and_base: 0x00000000001000000000000000007983
var_mask: 0x1c00000000000000ffffff00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDL.128
Load from local (thread-private stack) memory.
InsKey
Operands
Pipeline
Latency
LDL.128_R_ARI
R_ARI
MEMORY_LOCAL
100 ~
LDL.128_R_ARI — 2 fields · 12 samples
and_base: 0x0000000000100c000000000001007983
var_mask: 0x00000000000000000003f000000c0000
Bits
W
Tok
Extraction
[49:44]
6
t2
imm
[19:18]
2
t1
reg
LDL.64
Load from local (thread-private stack) memory.
InsKey
Operands
Pipeline
Latency
LDL.64_R_AR
R_AR
MEMORY_LOCAL
100 ~
LDL.64_R_ARI
R_ARI
MEMORY_LOCAL
100 ~
LDL.64_R_ARI_II
R_ARI_II
MEMORY_LOCAL
100 ~
LDL.64_R_AR_II
R_AR_II
MEMORY_LOCAL
100 ~
2 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDL.64_R_ARI_II_?
R_ARI_II_?
MEMORY_LOCAL
100 ~
LDL.64_R_AR_II_?
R_AR_II_?
MEMORY_LOCAL
100 ~
LDL.64_R_ARI_II_? — 2 fields · 10 samples
and_base: 0x0000000000100a000000000001047983
var_mask: 0x00000000000000000000380000080000
Bits
W
Tok
Extraction
[45:43]
3
t2
imm
[19]
1
t1
reg
LDL.64_R_AR — 2 fields · 32 samples
and_base: 0x0000000000100a000000000000007983
var_mask: 0x0000000000000000000000007f7e0000
Bits
W
Tok
Extraction
[30:24]
7
t2
reg
[22:17]
6
t1
reg
LDL.64_R_ARI — 2 fields · 32 samples
and_base: 0x0000000000100a000000000001007983
var_mask: 0x000000000000000000007800003e0000
Bits
W
Tok
Extraction
[46:43]
4
t2
imm
[21:17]
5
t1
reg
LDL.64_R_ARI_II — 2 fields · 5 samples
and_base: 0x0000000000100a000000000001007983
var_mask: 0x00000000000000000001f800001e0000
Bits
W
Tok
Extraction
[48:43]
6
t2
imm
[20:17]
4
t1
reg
LDL.64_R_AR_II — 2 fields · 1 samples
and_base: 0x0000000000100a000000000001007983
var_mask: 0x000000000000000000007800003e0000
Bits
W
Tok
Extraction
[46:43]
4
t2
imm
[21:17]
5
t1
reg
LDL.LU
Load from local (thread-private stack) memory.
InsKey
Operands
Pipeline
Latency
LDL.LU_R_AR
R_AR
MEMORY_LOCAL
100 ~
LDL.LU_R_ARI
R_ARI
MEMORY_LOCAL
100 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDL.LU_R_AR_?
R_AR_?
MEMORY_LOCAL
100 ~
LDL.LU_R_AR_? — 1 fields · 2 samples
and_base: 0x00000000003008000000000001057983
var_mask: 0x00000000000000000000000000020000
Bits
W
Tok
Extraction
[17]
1
t1
reg
LDL.LU_R_AR — 1 fields · 31 samples
and_base: 0x00000000003008000000000001007983
var_mask: 0x00000000000000000000000000ff0000
Bits
W
Tok
Extraction
[23:16]
8
t1
reg
LDL.LU_R_ARI — 2 fields · 32 samples
and_base: 0x00000000003008000000000001007983
var_mask: 0x00000000000000000000fc00007f0000
Bits
W
Tok
Extraction
[47:42]
6
t2
imm
[22:16]
7
t1
reg
LDL.LU.64
Load from local (thread-private stack) memory.
InsKey
Operands
Pipeline
Latency
LDL.LU.64_R_AR
R_AR
MEMORY_LOCAL
100 ~
LDL.LU.64_R_ARI
R_ARI
MEMORY_LOCAL
100 ~
LDL.LU.64_R_ARI_II
R_ARI_II
MEMORY_LOCAL
100 ~
LDL.LU.64_R_AR_II
R_AR_II
MEMORY_LOCAL
100 ~
LDL.LU.64_R_AR — 1 fields · 32 samples
and_base: 0x0000000000300a000000000001007983
var_mask: 0x000000000000000000000000007e0000
Bits
W
Tok
Extraction
[22:17]
6
t1
reg
LDL.LU.64_R_ARI — 2 fields · 32 samples
and_base: 0x0000000000300a000000000001007983
var_mask: 0x000000000000000000007800007e0000
Bits
W
Tok
Extraction
[46:43]
4
t2
imm
[22:17]
6
t1
reg
LDL.LU.64_R_ARI_II — 2 fields · 2 samples
and_base: 0x0000000000300a000000000001007983
var_mask: 0x000000000000000000001800000e0000
Bits
W
Tok
Extraction
[44:43]
2
t2
imm
[19:17]
3
t1
reg
LDL.LU.64_R_AR_II — 2 fields · 1 samples
and_base: 0x0000000000300a000000000001007983
var_mask: 0x000000000000000000007800007e0000
Bits
W
Tok
Extraction
[46:43]
4
t2
imm
[22:17]
6
t1
reg
LDL.S8
Load from local (thread-private stack) memory.
InsKey
Operands
Pipeline
Latency
LDL.S8_R_AR
R_AR
MEMORY_LOCAL
100 ~
LDL.S8_R_ARI
R_ARI
MEMORY_LOCAL
100 ~
LDL.S8_R_AR — 2 fields · 1 samples
and_base: 0x0000000000100200000000000a007983
var_mask: 0x000000000000000000000300000f0000
Bits
W
Tok
Extraction
[41:40]
2
t2
imm
[19:16]
4
t1
reg
LDL.S8_R_ARI — 2 fields · 16 samples
and_base: 0x0000000000100200000000000a007983
var_mask: 0x000000000000000000000300000f0000
Bits
W
Tok
Extraction
[41:40]
2
t2
imm
[19:16]
4
t1
reg
LDL.U8
Load from local (thread-private stack) memory.
InsKey
Operands
Pipeline
Latency
LDL.U8_R_ARI
R_ARI
MEMORY_LOCAL
100 ~
LDS
Load from shared memory. ~20–30 cycle latency.
InsKey
Operands
Modifiers
Pipeline
Latency
LDS_P_R_A
P_R_A
—
MEMORY_SHARED
30 ~
LDS_R_AR
R_AR
—
MEMORY_SHARED
30 ~
LDS_R_ARI
R_ARI
128, 64, U8
MEMORY_SHARED
30 ~
LDS_R_ARI_II
R_ARI_II
—
MEMORY_SHARED
30 ~
LDS_R_ARURI
R_ARURI
128, 64, U8
MEMORY_SHARED
30 ~
LDS_R_ARURI_R
R_ARURI_R
—
MEMORY_SHARED
30 ~
LDS_R_AR_R
R_AR_R
—
MEMORY_SHARED
30 ~
LDS_R_AUR
R_AUR
—
MEMORY_SHARED
30 ~
LDS_R_AURR
R_AURR
—
MEMORY_SHARED
30 ~
5 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDS_R_ARI_II_?
R_ARI_II_?
MEMORY_SHARED
30 ~
LDS_R_ARI_II_II_?
R_ARI_II_II_?
MEMORY_SHARED
30 ~
LDS_R_ARI_II_II_II_?
R_ARI_II_II_II_?
MEMORY_SHARED
30 ~
LDS_R_AR_II_?
R_AR_II_?
MEMORY_SHARED
30 ~
LDS_R_AR_II_II_?
R_AR_II_II_?
MEMORY_SHARED
30 ~
LDS_R_ARI_II_? — 3 fields · 32 samples
and_base: 0x00000000000008000000000000007984
var_mask: 0x0000000000000000fffff8007f7f0000
Bits
W
Tok
Extraction
[63:43]
21
t2
imm
[30:24]
7
t2
reg
[22:16]
7
t1
reg
LDS_R_ARI_II_II_? — 3 fields · 21 samples
and_base: 0x00000000000008000000000000017984
var_mask: 0x00000000000000000007f0007f1e0000
Bits
W
Tok
Extraction
[50:44]
7
t2
imm
[30:24]
7
t2
reg
[20:17]
4
t1
reg
LDS_R_ARI_II_II_II_? — 2 fields · 32 samples
and_base: 0x00000000000008000000000009007984
var_mask: 0x000000000000000000000c00000f0000
Bits
W
Tok
Extraction
[43:42]
2
t2
imm
[19:16]
4
t1
reg
LDS_R_AR_II_? — 2 fields · 32 samples
and_base: 0x00000000000008000000000000007984
var_mask: 0x0000000000000000000000003f3f0000
Bits
W
Tok
Extraction
[29:24]
6
t2
reg
[21:16]
6
t1
reg
LDS_R_AR_II_II_? — 2 fields · 32 samples
and_base: 0x00000000000008000000000000007984
var_mask: 0x0000000000000000000000003f0f0000
Bits
W
Tok
Extraction
[29:24]
6
t2
reg
[19:16]
4
t1
reg
LDS_P_R_A — 2 fields
and_base: 0xffff0984
var_mask: 0x1c00000000000000ffffff000000f000
Bits
W
Tok
Extraction
[63:40]
24
t2
imm
[15:12]
4
t0
guard
LDS_R_AR — 5 fields
and_base: 0x984
var_mask: 0x1c00000000000000ffffff00fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDS_R_ARI — 4 fields · 664 samples
and_base: 0x00000000000008000000000000007984
var_mask: 0x1c00000000000000ffffff00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDS_R_ARI.128 — 6 fields
and_base: 0x0000000000000c000000000000000984
var_mask: 0x1ffffe0000000000ffffff90fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
[15]
1
t0
imm
[15:12]
4
t0
guard
LDS_R_ARI.64 — 6 fields · 4 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x1c00000000000000ffffffd8ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[39:38]
2
t0
guard_neg
[36:35]
2
t0
guard_neg
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDS_R_ARI.U8 — 4 fields · 143 samples
and_base: 0x00000000000000000000000000007984
var_mask: 0x1c00000000000000ffffff00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDS_R_ARI_II — 3 fields · 32 samples
and_base: 0x00000000000008000000000000007984
var_mask: 0x0000000000000000fffffc007f1f0000
Bits
W
Tok
Extraction
[63:42]
22
t2
imm
[30:24]
7
t2
reg
[20:16]
5
t1
reg
LDS_R_ARURI — 3 fields · 2 samples
and_base: 0x00000000080008000000000408087984
var_mask: 0x1c0000000000000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDS_R_ARURI.128 — 5 fields · 3 samples
and_base: 0x0000000008000c000060000400008984
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t1
reuse
[39:32]
8
t2
sub_ur1
[31:24]
8
t1
reg
[23:16]
8
t1
reg
LDS_R_ARURI.64 — 5 fields · 1 samples
and_base: 0x0000000008000a000000000000007984
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t1
reuse
[39:32]
8
t2
sub_ur1
[31:24]
8
t1
reg
[23:16]
8
t1
reg
LDS_R_ARURI.U8 — 4 fields · 143 samples
and_base: 0x00000000000000000000000000007984
var_mask: 0x1c00000000000000ffffff00ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
LDS_R_ARURI_R — 6 fields · 1 samples
and_base: 0x00000000080008000000000400000984
var_mask: 0x1ffffe0000000000ffffff90fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[63:40]
24
t2
sub_imm1
[31:24]
8
t2
sub_r0
[23:16]
8
t1
reg
[15]
1
t0
imm
[15:12]
4
t0
guard
LDS_R_AR_R — 3 fields · 32 samples
and_base: 0x00000000000008000000000000000984
var_mask: 0x0000000000000000000000007f0ff000
Bits
W
Tok
Extraction
[30:24]
7
t2
reg
[19:16]
4
t1
reg
[15:12]
4
t0
guard
LDS_R_AUR — 4 fields
and_base: 0x800000000000000ff000984
var_mask: 0x1c00000000000000ffffffff00fff000
Bits
W
Tok
Extraction
[63:40]
24
t2
imm
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDS_R_AURR — 5 fields
and_base: 0x80000000000000000000984
var_mask: 0x1c00000000000000fffffffffffff000
Bits
W
Tok
Extraction
[63:40]
24
t2
imm
[39:32]
8
t2
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDS.128
Load from shared memory. ~20–30 cycle latency.
InsKey
Operands
Pipeline
Latency
LDS.128_R_AR
R_AR
MEMORY_SHARED
30 ~
LDS.128_R_ARI
R_ARI
MEMORY_SHARED
30 ~
LDS.128_R_ARI_II
R_ARI_II
MEMORY_SHARED
30 ~
LDS.128_R_ARUR
R_ARUR
MEMORY_SHARED
30 ~
LDS.128_R_ARURI
R_ARURI
MEMORY_SHARED
30 ~
LDS.128_R_ARURI_II
R_ARURI_II
MEMORY_SHARED
30 ~
LDS.128_R_AR_R
R_AR_R
MEMORY_SHARED
30 ~
LDS.128_R_AUR
R_AUR
MEMORY_SHARED
30 ~
LDS.128_R_AURI
R_AURI
MEMORY_SHARED
30 ~
8 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDS.128_R_ARI_II_?
R_ARI_II_?
MEMORY_SHARED
30 ~
LDS.128_R_ARI_II_II_?
R_ARI_II_II_?
MEMORY_SHARED
30 ~
LDS.128_R_ARI_II_II_II_?
R_ARI_II_II_II_?
MEMORY_SHARED
30 ~
LDS.128_R_ARURI_II_?
R_ARURI_II_?
MEMORY_SHARED
30 ~
LDS.128_R_ARURI_II_II_?
R_ARURI_II_II_?
MEMORY_SHARED
30 ~
LDS.128_R_AR_II_?
R_AR_II_?
MEMORY_SHARED
30 ~
LDS.128_R_AR_II_II_?
R_AR_II_II_?
MEMORY_SHARED
30 ~
LDS.128_R_AR_II_II_II_?
R_AR_II_II_II_?
MEMORY_SHARED
30 ~
LDS.128_R_ARI_II_? — 3 fields · 32 samples
and_base: 0x0000000000000c000000000000007984
var_mask: 0x0000000000000000fffff0007f7c0000
Bits
W
Tok
Extraction
[63:44]
20
t2
imm
[30:24]
7
t2
reg
[22:18]
5
t1
reg
LDS.128_R_ARI_II_II_? — 3 fields · 20 samples
and_base: 0x0000000000000c000000000000007984
var_mask: 0x0000000000000000003ff0007f3c0000
Bits
W
Tok
Extraction
[53:44]
10
t2
imm
[30:24]
7
t2
reg
[21:18]
4
t1
reg
LDS.128_R_ARI_II_II_II_? — 3 fields · 7 samples
and_base: 0x0000000000000c000000000008007984
var_mask: 0x00000000000000000007f000041c0000
Bits
W
Tok
Extraction
[50:44]
7
t2
imm
[26]
1
t2
reg
[20:18]
3
t1
reg
LDS.128_R_ARURI_II_? — 4 fields · 32 samples
and_base: 0x0000000008000c000000000000007984
var_mask: 0x00000000000000000000101fff3c0000
Bits
W
Tok
Extraction
[44]
1
t2
imm
[36:32]
5
t2
ureg
[31:24]
8
t2
reg
[21:18]
4
t1
reg
LDS.128_R_ARURI_II_II_? — 4 fields · 19 samples
and_base: 0x0000000008000c000000000000007984
var_mask: 0x00000000000000000004001f3f3c0000
Bits
W
Tok
Extraction
[50]
1
t2
imm
[36:32]
5
t2
ureg
[29:24]
6
t2
reg
[21:18]
4
t1
reg
LDS.128_R_AR_II_? — 2 fields · 32 samples
and_base: 0x0000000000000c000000000000007984
var_mask: 0x0000000000000000000000003f1c0000
Bits
W
Tok
Extraction
[29:24]
6
t2
reg
[20:18]
3
t1
reg
LDS.128_R_AR_II_II_? — 2 fields · 29 samples
and_base: 0x0000000000000c000000000000007984
var_mask: 0x0000000000000000000000007f7c0000
Bits
W
Tok
Extraction
[30:24]
7
t2
reg
[22:18]
5
t1
reg
LDS.128_R_AR — 4 fields
and_base: 0x984
var_mask: 0x1c00000000000000ffffff00fffff000
Bits
W
Tok
Extraction
[63:40]
24
t2
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDS.128_R_ARI — 2 fields · 32 samples
and_base: 0x0000000000000c000002000080007984
var_mask: 0x0000000000000000000000003ffc0000
Bits
W
Tok
Extraction
[29:24]
6
t2
reg
[23:18]
6
t1
reg
LDS.128_R_ARI_II — 3 fields · 32 samples
and_base: 0x0000000000000c000000000000007984
var_mask: 0x0000000000000000003ff0007f1c0000
Bits
W
Tok
Extraction
[53:44]
10
t2
imm
[30:24]
7
t2
reg
[20:18]
3
t1
reg
LDS.128_R_ARUR — 5 fields
and_base: 0x80000000000000000000984
var_mask: 0x1c00000000000000fffffffffffff000
Bits
W
Tok
Extraction
[63:40]
24
t2
imm
[39:32]
8
t2
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDS.128_R_ARURI — 2 fields · 32 samples
and_base: 0x0000000008000c0000000007a2007984
var_mask: 0x00000000000000000003000000fc0000
Bits
W
Tok
Extraction
[49:48]
2
t2
imm
[23:18]
6
t1
reg
LDS.128_R_ARURI_II — 4 fields · 32 samples
and_base: 0x0000000008000c000000000000007984
var_mask: 0x0000000000000000003ff00fff1c0000
Bits
W
Tok
Extraction
[53:44]
10
t2
imm
[35:32]
4
t2
ureg
[31:24]
8
t2
reg
[20:18]
3
t1
reg
LDS.128_R_AR_R — 3 fields · 32 samples
and_base: 0x0000000000000c000000000000000984
var_mask: 0x0000000000000000000000003f1cf000
Bits
W
Tok
Extraction
[29:24]
6
t2
reg
[20:18]
3
t1
reg
[15:12]
4
t0
guard
LDS.128_R_AUR — 5 fields
and_base: 0x800000000000000ff000984
var_mask: 0x1c00000000000000ffffffff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[63:40]
24
t2
imm
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDS.128_R_AURI — 5 fields
and_base: 0x800000000000000ff000984
var_mask: 0x1c00000000000000ffffffff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[63:40]
24
t2
imm
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDS.64
Load from shared memory. ~20–30 cycle latency.
InsKey
Operands
Pipeline
Latency
LDS.64_R_AR
R_AR
MEMORY_SHARED
30 ~
LDS.64_R_ARI
R_ARI
MEMORY_SHARED
30 ~
LDS.64_R_ARI_II
R_ARI_II
MEMORY_SHARED
30 ~
LDS.64_R_ARURI
R_ARURI
MEMORY_SHARED
30 ~
LDS.64_R_ARURI_II
R_ARURI_II
MEMORY_SHARED
30 ~
LDS.64_R_AR_R
R_AR_R
MEMORY_SHARED
30 ~
LDS.64_R_AUR
R_AUR
MEMORY_SHARED
30 ~
7 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
LDS.64_R_ARI_II_?
R_ARI_II_?
MEMORY_SHARED
30 ~
LDS.64_R_ARI_II_II_?
R_ARI_II_II_?
MEMORY_SHARED
30 ~
LDS.64_R_ARI_II_II_II_?
R_ARI_II_II_II_?
MEMORY_SHARED
30 ~
LDS.64_R_ARURI_II_?
R_ARURI_II_?
MEMORY_SHARED
30 ~
LDS.64_R_AR_II_?
R_AR_II_?
MEMORY_SHARED
30 ~
LDS.64_R_AR_II_II_?
R_AR_II_II_?
MEMORY_SHARED
30 ~
LDS.64_R_AR_II_II_II_?
R_AR_II_II_II_?
MEMORY_SHARED
30 ~
LDS.64_R_ARI_II_? — 3 fields · 32 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x000000000000000000fff8007ffe0000
Bits
W
Tok
Extraction
[55:43]
13
t2
imm
[30:24]
7
t2
reg
[23:17]
7
t1
reg
LDS.64_R_ARI_II_II_? — 3 fields · 13 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x0000000000000000001ff0003f3e0000
Bits
W
Tok
Extraction
[52:44]
9
t2
imm
[29:24]
6
t2
reg
[21:17]
5
t1
reg
LDS.64_R_ARI_II_II_II_? — 3 fields · 32 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x0000000000000000000018001e3e0000
Bits
W
Tok
Extraction
[44:43]
2
t2
imm
[28:25]
4
t2
reg
[21:17]
5
t1
reg
LDS.64_R_ARURI_II_? — 4 fields · 1 samples
and_base: 0x0000000008000a000000000400007984
var_mask: 0x00000000000000000007f801ff0e0000
Bits
W
Tok
Extraction
[50:43]
8
t2
imm
[32]
1
t2
ureg
[31:24]
8
t2
reg
[19:17]
3
t1
reg
LDS.64_R_AR_II_? — 2 fields · 32 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x0000000000000000000000000f7e0000
Bits
W
Tok
Extraction
[27:24]
4
t2
reg
[22:17]
6
t1
reg
LDS.64_R_AR_II_II_? — 2 fields · 32 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x0000000000000000000000007f7e0000
Bits
W
Tok
Extraction
[30:24]
7
t2
reg
[22:17]
6
t1
reg
LDS.64_R_AR_II_II_II_? — 1 fields · 6 samples
and_base: 0x0000000000000a0000000000000e7984
var_mask: 0x0000000000000000000000003f000000
Bits
W
Tok
Extraction
[29:24]
6
t2
reg
LDS.64_R_AR — 2 fields · 32 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x0000000000000000000000003f1e0000
Bits
W
Tok
Extraction
[29:24]
6
t2
reg
[20:17]
4
t1
reg
LDS.64_R_ARI — 3 fields · 32 samples
and_base: 0x0000000000000a000000100000007984
var_mask: 0x0000000000000000000040007f7e0000
Bits
W
Tok
Extraction
[46]
1
t2
imm
[30:24]
7
t2
reg
[22:17]
6
t1
reg
LDS.64_R_ARI_II — 3 fields · 32 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x0000000000000000fffff8007ffe0000
Bits
W
Tok
Extraction
[63:43]
21
t2
imm
[30:24]
7
t2
reg
[23:17]
7
t1
reg
LDS.64_R_ARURI — 3 fields · 32 samples
and_base: 0x0000000008000a000000000420007984
var_mask: 0x0000000000000000003fc0001f3e0000
Bits
W
Tok
Extraction
[53:46]
8
t2
imm
[28:24]
5
t2
reg
[21:17]
5
t1
reg
LDS.64_R_ARURI_II — 4 fields · 11 samples
and_base: 0x0000000008000a000000000400007984
var_mask: 0x00000000000000000007f801ff0e0000
Bits
W
Tok
Extraction
[50:43]
8
t2
imm
[32]
1
t2
ureg
[31:24]
8
t2
reg
[19:17]
3
t1
reg
LDS.64_R_AR_R — 2 fields · 32 samples
and_base: 0x0000000000000a000000000000007984
var_mask: 0x0000000000000000000000007f3e0000
Bits
W
Tok
Extraction
[30:24]
7
t2
reg
[21:17]
5
t1
reg
LDS.64_R_AUR — 2 fields · 29 samples
and_base: 0x0000000008000a0000000000ff007984
var_mask: 0x00000000000000000000000e000e0000
Bits
W
Tok
Extraction
[35:33]
3
t2
ureg
[19:17]
3
t1
reg
LDS.S8
Load from shared memory. ~20–30 cycle latency.
InsKey
Operands
Pipeline
Latency
LDS.S8_R_AR
R_AR
MEMORY_SHARED
30 ~
LDS.S8_R_ARURI
R_ARURI
MEMORY_SHARED
30 ~
LDS.S8_R_AR — 2 fields · 32 samples
and_base: 0x00000000000002000000000000407984
var_mask: 0x0000000000000000000000007f3f0000
Bits
W
Tok
Extraction
[30:24]
7
t2
reg
[21:16]
6
t1
reg
LDS.S8_R_ARURI — 3 fields · 32 samples
and_base: 0x00000000080002000000000000407984
var_mask: 0x00000000000000000000001f7f3f0000
Bits
W
Tok
Extraction
[36:32]
5
t2
ureg
[30:24]
7
t2
reg
[21:16]
6
t1
reg
LDS.U16
Load from shared memory. ~20–30 cycle latency.
InsKey
Operands
Pipeline
Latency
LDS.U16_R_AR
R_AR
MEMORY_SHARED
30 ~
LDS.U16_R_ARI
R_ARI
MEMORY_SHARED
30 ~
LDS.U16_R_ARURI
R_ARURI
MEMORY_SHARED
30 ~
LDS.U16_R_AR — 2 fields · 32 samples
and_base: 0x00000000000004000000000000007984
var_mask: 0x0000000000000000000000003f3f0000
Bits
W
Tok
Extraction
[29:24]
6
t2
reg
[21:16]
6
t1
reg
LDS.U16_R_ARI — 3 fields · 32 samples
and_base: 0x00000000000004000000000000007984
var_mask: 0x0000000000000000fffff0000e1f0000
Bits
W
Tok
Extraction
[63:44]
20
t2
imm
[27:25]
3
t2
reg
[20:16]
5
t1
reg
LDS.U16_R_ARURI — 3 fields · 32 samples
and_base: 0x00000000080004000000000000007984
var_mask: 0x00000000000000000000001e3f3f0000
Bits
W
Tok
Extraction
[36:33]
4
t2
ureg
[29:24]
6
t2
reg
[21:16]
6
t1
reg
LDS.U8
Load from shared memory. ~20–30 cycle latency.
InsKey
Operands
Pipeline
Latency
LDS.U8_R_AR
R_AR
MEMORY_SHARED
30 ~
LDS.U8_R_ARI
R_ARI
MEMORY_SHARED
30 ~
LDS.U8_R_AR — 2 fields · 32 samples
and_base: 0x00000000000000000000000000007984
var_mask: 0x0000000000000000000000007f7f0000
Bits
W
Tok
Extraction
[30:24]
7
t2
reg
[22:16]
7
t1
reg
LDS.U8_R_ARI — 3 fields · 32 samples
and_base: 0x00000000000000000000000000007984
var_mask: 0x00000000000000000001f8007f7f0000
Bits
W
Tok
Extraction
[48:43]
6
t2
imm
[30:24]
7
t2
reg
[22:16]
7
t1
reg
LDSM
Load from shared memory in matrix layout (ldmatrix). Loads a matrix tile from shared memory into tensor core register layout. Used before HMMA/IMMA as an efficient alternative to individual LDS instructions.
InsKey
Operands
Modifiers
Pipeline
Latency
LDSM_R_ARI
R_ARI
16,4,MT88, 16,4,M88
MEMORY_SHARED
30 ~
LDSM_R_ARURI
R_ARURI
16,4,MT88, 16,4,M88
MEMORY_SHARED
30 ~
LDSM_R_ARI.16,4,MT88 — 6 fields · 77 samples
and_base: 0x8004200000000000040783b
var_mask: 0x1c000000000000000038001f7f3c0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t2
reuse
[53:51]
3
t0
[36:32]
5
t2
ureg
[30:24]
7
t2
reg
[21:18]
4
t0
LDSM_R_ARI.16,4,M88 — 7 fields · 73 samples
and_base: 0x200000000000040783b
var_mask: 0x1c0000000800000000780007a73c0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[91]
1
t3
imm
[54:51]
4
t0
[34:31]
4
t0
[29]
1
t1
reg
[26:24]
3
t2
reg
[21:18]
4
t0
LDSM_R_ARURI.16,4,MT88 — 13 fields · 77 samples
and_base: 0x8000000000000000000083b
var_mask: 0x1c0000000801cb00ffffff1703fff000
Bits
W
Tok
Extraction
[91]
1
t2
[80]
1
t1
reg
[79]
1
t1
reg
[78]
1
t0
neg
[75]
1
t1
reg
[73]
1
t0
neg
[72]
1
t1
reg
[63:40]
24
t2
imm
[36]
1
t1
reg
[34:32]
3
t4
imm
[25:24]
2
t3
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDSM_R_ARURI.16,4,M88 — 13 fields · 73 samples
and_base: 0x8000000000000000000083b
var_mask: 0x1c0000000801cb00ffffff1703fff000
Bits
W
Tok
Extraction
[91]
1
t2
[80]
1
t1
reg
[79]
1
t1
reg
[78]
1
t1
reg
[75]
1
t1
reg
[73]
1
t0
neg
[72]
1
t1
reg
[63:40]
24
t2
imm
[36]
1
t1
reg
[34:32]
3
t4
imm
[25:24]
2
t3
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDSM.16.M88
Load from shared memory in matrix layout (ldmatrix). Loads a matrix tile from shared memory into tensor core register layout. Used before HMMA/IMMA as an efficient alternative to individual LDS instructions.
InsKey
Operands
Pipeline
Latency
LDSM.16.M88_R_AUR
R_AUR
MEMORY_SHARED
30 ~
LDSM.16.M88_R_AUR — 5 fields
and_base: 0x800000000000000ff00083b
var_mask: 0x1c00000000000000ffffffff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[63:40]
24
t2
imm
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LDSM.16.M88.2
Load from shared memory in matrix layout (ldmatrix). Loads a matrix tile from shared memory into tensor core register layout. Used before HMMA/IMMA as an efficient alternative to individual LDS instructions.
InsKey
Operands
Pipeline
Latency
LDSM.16.M88.2_R_AR
R_AR
MEMORY_SHARED
30 ~
LDSM.16.M88.2_R_AR — 2 fields · 32 samples
and_base: 0x0000000000000100000000000000783b
var_mask: 0x0000000000000000000000007f7e0000
Bits
W
Tok
Extraction
[30:24]
7
t2
reg
[22:17]
6
t1
reg
LDSM.16.M88.4
Load from shared memory in matrix layout (ldmatrix). Loads a matrix tile from shared memory into tensor core register layout. Used before HMMA/IMMA as an efficient alternative to individual LDS instructions.
InsKey
Operands
Pipeline
Latency
LDSM.16.M88.4_R_AR
R_AR
MEMORY_SHARED
30 ~
LDSM.16.M88.4_R_ARI
R_ARI
MEMORY_SHARED
30 ~
LDSM.16.M88.4_R_ARURI
R_ARURI
MEMORY_SHARED
30 ~
LDSM.16.M88.4_R_AR — 2 fields · 32 samples
and_base: 0x0000000000000200000000000000783b
var_mask: 0x000000000000000000000000fffc0000
Bits
W
Tok
Extraction
[31:24]
8
t2
reg
[23:18]
6
t1
reg
LDSM.16.M88.4_R_ARI — 3 fields · 32 samples
and_base: 0x0000000000000200000000000080783b
var_mask: 0x000000000000000000780000ff3c0000
Bits
W
Tok
Extraction
[54:51]
4
t2
imm
[31:24]
8
t2
reg
[21:18]
4
t1
reg
LDSM.16.M88.4_R_ARURI — 4 fields · 32 samples
and_base: 0x0000000008000200000000000080783b
var_mask: 0x00000000000000000078000fff7c0000
Bits
W
Tok
Extraction
[54:51]
4
t2
imm
[35:32]
4
t2
ureg
[31:24]
8
t2
reg
[22:18]
5
t1
reg
LDSM.16.MT88.4
Load from shared memory in matrix layout (ldmatrix). Loads a matrix tile from shared memory into tensor core register layout. Used before HMMA/IMMA as an efficient alternative to individual LDS instructions.
InsKey
Operands
Pipeline
Latency
LDSM.16.MT88.4_R_AR
R_AR
MEMORY_SHARED
30 ~
LDSM.16.MT88.4_R_ARURI
R_ARURI
MEMORY_SHARED
30 ~
LDSM.16.MT88.4_R_ARURI — 4 fields · 32 samples
and_base: 0x0000000008004200000000000080783b
var_mask: 0x00000000000000000030000fff7c0000
Bits
W
Tok
Extraction
[53:52]
2
t2
imm
[35:32]
4
t2
ureg
[31:24]
8
t2
reg
[22:18]
5
t1
reg
LEA
Load effective address. Rd = Ra + (Rb << imm). Primary instruction for pointer arithmetic and address calculation.
InsKey
Operands
Modifiers
Pipeline
Latency
LEA_P0_R_R_R_II
P0_R_R_R_II
—
INT_ARITH
4 ★
LEA_R_P_R_II_II
R_P_R_II_II
HI,SX32,X, HI, HI,X
INT_ARITH
4 ★
LEA_R_P_R_R_II
R_P_R_R_II
HI,SX32,X, HI, HI,X
INT_ARITH
4 ★
LEA_R_P_R_R_II_II
R_P_R_R_II_II
—
INT_ARITH
4 ★
LEA_R_P_R_R_II_P
R_P_R_R_II_P
HI,SX32,X, HI, HI,X
INT_ARITH
4 ★
LEA_R_P_R_UR_II
R_P_R_UR_II
HI,SX32,X, HI, HI,X
INT_ARITH
4 ★
LEA_R_R_II_II
R_R_II_II
HI,SX32,X, HI, HI,X
INT_ARITH
4 ★
LEA_R_R_II_II_II
R_R_II_II_II
—
INT_ARITH
4 ★
LEA_R_R_II_R_II
R_R_II_R_II
HI, HI,SX32,X, HI,X
INT_ARITH
4 ★
LEA_R_R_II_R_II_P
R_R_II_R_II_P
HI,X, HI,SX32,X, HI
INT_ARITH
4 ★
LEA_R_R_R_II
R_R_R_II
HI,SX32,X, HI, HI,X
INT_ARITH
4 ★
LEA_R_R_R_II_II
R_R_R_II_II
—
INT_ARITH
4 ★
LEA_R_R_R_II_P
R_R_R_II_P
HI,SX32,X, HI, HI,X
INT_ARITH
4 ★
LEA_R_R_R_R_II
R_R_R_R_II
HI, HI,SX32,X, HI,X
INT_ARITH
4 ★
LEA_R_R_R_R_II_P
R_R_R_R_II_P
HI,X, HI,SX32,X, HI
INT_ARITH
4 ★
LEA_R_R_UR_II
R_R_UR_II
HI,SX32,X, HI, HI,X
INT_ARITH
4 ★
LEA_R_R_UR_II_II
R_R_UR_II_II
—
INT_ARITH
4 ★
LEA_R_R_UR_R_II
R_R_UR_R_II
HI, HI,SX32,X, HI,X
INT_ARITH
4 ★
LEA_R_R_UR_R_II_P
R_R_UR_R_II_P
HI,X, HI,SX32,X, HI
INT_ARITH
4 ★
15 partial encodings — operand types not fully identified
3-input bitwise logical operation. Rd = f(Ra, Rb, Rc) where f is defined by an 8-bit LUT immediate. Can express any of the 256 possible Boolean functions of three inputs. The .LUT suffix is always present in SM120 SASS.
InsKey
Operands
Modifiers
Pipeline
Latency
LOP3_P_R_R_II_R_II_P
P_R_R_II_R_II_P
LUT
INT_ARITH
4 ★
LOP3_P_R_R_R_R_II_P
P_R_R_R_R_II_P
LUT
INT_ARITH
4 ★
LOP3_P_R_R_UR_R_II_P
P_R_R_UR_R_II_P
LUT
INT_ARITH
4 ★
LOP3_R_R_II_R_II_P
R_R_II_R_II_P
LUT
INT_ARITH
4 ★
LOP3_R_R_R_R_II_P
R_R_R_R_II_P
LUT
INT_ARITH
4 ★
LOP3_R_R_UR_R_II_P
R_R_UR_R_II_P
LUT
INT_ARITH
4 ★
LOP3_P_R_R_II_R_II_P.LUT — 8 fields · 165 samples
and_base: 0x000000000780c0ff0000000000001812
var_mask: 0x1c000000038e0000fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[89:87]
3
t7
pred
[83:81]
3
t1
pred
[79:72]
8
t6
imm
[63:32]
32
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t2
reg
[15:12]
4
t0
guard
LOP3_P_R_R_R_R_II_P.LUT — 8 fields · 76 samples
and_base: 0x000000000780c00e0000000000ff7212
var_mask: 0x1c000000000e3cff000000ffff000000
Bits
W
Tok
Extraction
[124]
1
t5
reuse
[123]
1
t4
reuse
[122]
1
t3
reuse
[83:81]
3
t1
pred
[79:72]
8
t6
imm
[71:64]
8
t5
reg
[39:32]
8
t4
reg
[31:24]
8
t3
reg
LOP3_P_R_R_UR_R_II_P.LUT — 12 fields
and_base: 0x00000000080000000000000000000c12
var_mask: 0x1ffffe00078effff000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t5
reuse
[123]
1
t4
reuse
[122]
1
t3
reuse
[90]
1
t7
inv
[89:87]
3
t7
pred
[83:81]
3
t1
pred
[79:72]
8
t6
imm
[71:64]
8
t5
reg
[39:32]
8
t4
ureg
[31:24]
8
t3
reg
[23:16]
8
t2
reg
[15:12]
4
t0
guard
LOP3_R_R_II_R_II_P.LUT — 8 fields · 2,437 samples
and_base: 0x00000000078e00000000000000000812
var_mask: 0x1c0000000000fefffffffffffffff000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[122]
1
t2
reuse
[79:72]
8
t5
imm
[71:64]
8
t4
reg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LOP3_R_R_R_R_II_P.LUT — 9 fields · 40,683 samples
and_base: 0x00000000078e00000000000000000212
var_mask: 0x1c0000000000ffff000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[79:72]
8
t5
imm
[71:64]
8
t4
reg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LOP3_R_R_UR_R_II_P.LUT — 10 fields · 533 samples
and_base: 0x000000000f8000000000000000000c12
var_mask: 0x1c000000000effff000000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
reuse
[122]
1
t2
reuse
[83:81]
3
t6
pred
[79:72]
8
t5
imm
[71:64]
8
t4
reg
[39:32]
8
t3
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
LOP3.LUT
3-input bitwise logical operation. Rd = f(Ra, Rb, Rc) where f is defined by an 8-bit LUT immediate. Can express any of the 256 possible Boolean functions of three inputs. The .LUT suffix is always present in SM120 SASS.
InsKey
Operands
Pipeline
Latency
LOP3.LUT_P_R_R_II_R_II_P
P_R_R_II_R_II_P
INT_ARITH
4 ★
LOP3.LUT_P_R_R_R_R_II_II
P_R_R_R_R_II_II
INT_ARITH
4 ★
LOP3.LUT_P_R_R_R_R_II_P
P_R_R_R_R_II_P
INT_ARITH
4 ★
LOP3.LUT_P_R_R_UR_R_II_P
P_R_R_UR_R_II_P
INT_ARITH
4 ★
LOP3.LUT_R_R_II_R_II_II
R_R_II_R_II_II
INT_ARITH
4 ★
LOP3.LUT_R_R_II_R_II_P
R_R_II_R_II_P
INT_ARITH
4 ★
LOP3.LUT_R_R_R_R_II_II
R_R_R_R_II_II
INT_ARITH
4 ★
LOP3.LUT_R_R_R_R_II_P
R_R_R_R_II_P
INT_ARITH
4 ★
LOP3.LUT_R_R_UR_R_II_II
R_R_UR_R_II_II
INT_ARITH
4 ★
LOP3.LUT_R_R_UR_R_II_P
R_R_UR_R_II_P
INT_ARITH
4 ★
13 partial encodings — operand types not fully identified
Warp match broadcast. For each thread, determines which other threads in the warp hold the same value in Ra, and returns a lane mask. .ANY: any-match variant.
InsKey
Operands
Modifiers
Pipeline
Latency
MATCH_R_R
R_R
ANY
WARP_SYNC
4 ~
MATCH_R_R.ANY — 3 fields · 150 samples
and_base: 0xe800000000000000073a1
var_mask: 0x1c00000000000000000000003f0f0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[29:24]
6
t2
reg
[19:16]
4
t1
reg
MATCH.ANY
Warp match broadcast. For each thread, determines which other threads in the warp hold the same value in Ra, and returns a lane mask. .ANY: any-match variant.
InsKey
Operands
Pipeline
Latency
MATCH.ANY_R_R
R_R
WARP_SYNC
4 ~
MATCH.ANY_R_R — 4 fields
and_base: 0xe000000000000000003a1
var_mask: 0x1c0000000000000000000000fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MEMBAR
Memory barrier. Enforces ordering of memory operations. .GL: global scope.
InsKey
Operands
Modifiers
Pipeline
Latency
MEMBAR
GPU,SC
BARRIER
0 ~
MEMBAR.GPU,SC — 1 fields · 150 samples
and_base: 0x20000000000000007992
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
MEMBAR.ALL.CTA
Memory barrier. Enforces ordering of memory operations. .GL: global scope.
InsKey
Operands
Pipeline
Latency
MEMBAR.ALL.CTA
BARRIER
0 ~
MEMBAR.ALL.CTA — 1 fields
and_base: 0x992
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
MEMBAR.ALL.GPU
Memory barrier. Enforces ordering of memory operations. .GL: global scope.
InsKey
Operands
Pipeline
Latency
MEMBAR.ALL.GPU
BARRIER
0 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
MEMBAR.ALL.GPU_?
?
BARRIER
0 ~
MEMBAR.ALL.GPU — 1 fields
and_base: 0x992
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
MEMBAR.SC.CTA
Memory barrier. Enforces ordering of memory operations. .GL: global scope.
InsKey
Operands
Pipeline
Latency
MEMBAR.SC.CTA
BARRIER
0 ~
MEMBAR.SC.CTA — 1 fields
and_base: 0x992
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
MEMBAR.SC.GPU
Memory barrier. Enforces ordering of memory operations. .GL: global scope.
InsKey
Operands
Pipeline
Latency
MEMBAR.SC.GPU
BARRIER
0 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
MEMBAR.SC.GPU_?
?
BARRIER
0 ~
MEMBAR.SC.GPU — 1 fields
and_base: 0x992
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
MEMBAR.SC.SYS
Memory barrier. Enforces ordering of memory operations. .GL: global scope.
InsKey
Operands
Pipeline
Latency
MEMBAR.SC.SYS
BARRIER
0 ~
MEMBAR.SC.SYS — 1 fields
and_base: 0x992
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
MOV
Move. Copies a register value or loads an immediate into Rd.
InsKey
Operands
Modifiers
Pipeline
Latency
MOV_P0_R_II
P0_R_II
—
INT_ARITH
4 ★
MOV_P_R_II
P_R_II
—
INT_ARITH
4 ★
MOV_P_R_R
P_R_R
—
INT_ARITH
4 ★
MOV_R_II
R_II
64
INT_ARITH
4 ★
MOV_R_II_II
R_II_II
—
INT_ARITH
4 ★
MOV_R_R
R_R
64
INT_ARITH
4 ★
MOV_R_R_R
R_R_R
—
INT_ARITH
4 ★
MOV_R_UR
R_UR
64
INT_ARITH
4 ★
6 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
MOV_R_II_II_?
R_II_II_?
INT_ARITH
4 ★
MOV_R_R_II_?
R_R_II_?
INT_ARITH
4 ★
MOV_R_R_II_II_?
R_R_II_II_?
INT_ARITH
4 ★
MOV_R_R_II_II_II_?
R_R_II_II_II_?
INT_ARITH
4 ★
MOV_R_UR_II_?
R_UR_II_?
INT_ARITH
4 ★
MOV_R_UR_II_II_?
R_UR_II_II_?
INT_ARITH
4 ★
MOV_R_II_II_? — 3 fields · 5 samples
and_base: 0x0000000000000f000000000100010802
var_mask: 0x000000000000000000000002001e7000
Bits
W
Tok
Extraction
[33]
1
t2
imm
[20:17]
4
t1
reg
[14:12]
3
t0
guard
MOV_R_R_II_? — 3 fields · 32 samples
and_base: 0x0000000000000f000000000000001202
var_mask: 0x00000000000000000000007e000fe000
Bits
W
Tok
Extraction
[38:33]
6
t2
reg
[19:16]
4
t1
reg
[15:13]
3
t0
guard
MOV_R_R_II_II_? — 7 fields · 1 samples
and_base: 0x00000000000000000000000000000202
var_mask: 0x1c00000000fffffffffffffffffff000
Bits
W
Tok
Extraction
[87:76]
12
t2
imm_shr52
[75:72]
4
t2
imm_shr48
[71:64]
8
t2
imm_shr40
[63:32]
32
t2
imm_shr8
[31:24]
8
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV_R_R_II_II_II_? — 2 fields · 15 samples
and_base: 0x0000000000000f000000000000007202
var_mask: 0x0000000000000000000000ff001f0000
Bits
W
Tok
Extraction
[39:32]
8
t2
reg
[20:16]
5
t1
reg
MOV_R_UR_II_? — 2 fields · 32 samples
and_base: 0x0000000000000f000000000000007002
var_mask: 0x0000000008000000000000ff007f0e00
Bits
W
Tok
Extraction
[39:32]
8
t2
ureg
[22:16]
7
t1
reg
MOV_R_UR_II_II_? — 2 fields · 32 samples
and_base: 0x0000000000000f000000000000007002
var_mask: 0x0000000008000000000000ff003f0e00
Bits
W
Tok
Extraction
[39:32]
8
t2
ureg
[21:16]
6
t1
reg
MOV_P0_R_II — 4 fields
and_base: 0xf000000000000000802
var_mask: 0xffffffff00fff080
Bits
W
Tok
Extraction
[63:32]
32
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
[7]
1
t0
guard
MOV_P_R_II — 4 fields
and_base: 0xf000000000000000802
var_mask: 0x1c00000000000000ffffffff00fff080
Bits
W
Tok
Extraction
[63:32]
32
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
[7]
1
t0
guard
MOV_P_R_R — 7 fields
and_base: 0xf000000000000000202
var_mask: 0x1c00000000000000000000ff31fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t0
reuse
[39:32]
8
t2
reg
[29:28]
2
t0
reg
[24]
1
t0
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV_R_II — 3 fields · 1,347 samples
and_base: 0x0000000000000f000000000000000802
var_mask: 0x1c00000000000000ffffffff00fff000
Bits
W
Tok
Extraction
[63:32]
32
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV_R_II.64 — 7 fields · 55 samples
and_base: 0x00000000000000000000000000000402
var_mask: 0x1c00000000fffffffffffffffffff000
Bits
W
Tok
Extraction
[87:76]
12
t2
imm_shr52
[75:72]
4
t2
imm_shr48
[71:64]
8
t2
imm_shr40
[63:32]
32
t2
imm_shr8
[31:24]
8
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV_R_II_II — 2 fields · 32 samples
and_base: 0x0000000000000f000000000000007802
var_mask: 0x00000000000000003fffffff00ff0000
Bits
W
Tok
Extraction
[61:32]
30
t2
imm
[23:16]
8
t1
reg
MOV_R_R — 7 fields · 4,718 samples
and_base: 0x0000000000000f000000000000000202
var_mask: 0x1c00000000000000000000ff31fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t0
reuse
[39:32]
8
t2
reg
[29:28]
2
t0
reg
[24]
1
t0
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV_R_R.64 — 7 fields
and_base: 0x0000000000010f000000000000000202
var_mask: 0x1ffffe0000000000000000ff31fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t0
reuse
[39:32]
8
t2
reg
[29:28]
2
t0
reg
[24]
1
t0
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV_R_R_R — 2 fields · 32 samples
and_base: 0x0000000000000f000000000000007202
var_mask: 0x0000000000000000000000ff00ff0000
Bits
W
Tok
Extraction
[39:32]
8
t2
reg
[23:16]
8
t1
reg
MOV_R_UR — 4 fields · 480 samples
and_base: 0x0000000008000f000000000000000c02
var_mask: 0x1c00000000000000000000ff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV_R_UR.64 — 3 fields · 188 samples
and_base: 0x0000000008010f000000000000007c02
var_mask: 0x1c00000000000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
MOV.64
Move. Copies a register value or loads an immediate into Rd.
InsKey
Operands
Pipeline
Latency
MOV.64_R_II
R_II
INT_ARITH
4 ★
MOV.64_R_R
R_R
INT_ARITH
4 ★
MOV.64_R_UR
R_UR
INT_ARITH
4 ★
MOV.64_R_UR_UR
R_UR_UR
INT_ARITH
4 ★
3 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
MOV.64_R_II_?
R_II_?
INT_ARITH
4 ★
MOV.64_R_UR_II_?
R_UR_II_?
INT_ARITH
4 ★
MOV.64_R_UR_II_II_?
R_UR_II_II_?
INT_ARITH
4 ★
MOV.64_R_UR_II_? — 2 fields · 32 samples
and_base: 0x0000000000010f000000000000007002
var_mask: 0x0000000008000000000000ff00fe0e00
Bits
W
Tok
Extraction
[39:32]
8
t2
ureg
[23:17]
7
t1
reg
MOV.64_R_UR_II_II_? — 2 fields · 15 samples
and_base: 0x0000000000010f000000000000007002
var_mask: 0x0000000008000000000000ff003e0e00
Bits
W
Tok
Extraction
[39:32]
8
t2
ureg
[21:17]
5
t1
reg
MOV.64_R_II — 3 fields
and_base: 0x402
var_mask: 0x1c00000000fffffffffffffffffff000
Bits
W
Tok
Extraction
[87:24]
64
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV.64_R_R — 4 fields
and_base: 0xf000000000000000202
var_mask: 0x1c00000000000000000000ff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV.64_R_UR — 3 fields
and_base: 0x8000f000000000000000c02
var_mask: 0x1c00000000000000000000ff00fff000
Bits
W
Tok
Extraction
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOV.64_R_UR_UR — 2 fields · 32 samples
and_base: 0x0000000000010f000000000000007002
var_mask: 0x0000000008000000000000ff007e0e00
Bits
W
Tok
Extraction
[39:32]
8
t2
ureg
[22:17]
6
t1
reg
MOVM.16.MT88
Matrix data move (SM120). MOVM.16.MT88 moves 16-bit data using MT88 (8×8 bit-packed) format, used to rearrange data before QMMA/HMMA. Bridges between register file layout and tensor core operand layout.
InsKey
Operands
Pipeline
Latency
MOVM.16.MT88_P0_R_R
P0_R_R
MEMORY_SHARED
4 ~
MOVM.16.MT88_P2_R_R
P2_R_R
MEMORY_SHARED
4 ~
MOVM.16.MT88_P5_R_R
P5_R_R
MEMORY_SHARED
4 ~
MOVM.16.MT88_P_R_R
P_R_R
MEMORY_SHARED
4 ~
MOVM.16.MT88_R_R
R_R
MEMORY_SHARED
4 ~
MOVM.16.MT88_P0_R_R — 3 fields · 20 samples
and_base: 0x23a
var_mask: 0xfffff000
Bits
W
Tok
Extraction
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOVM.16.MT88_P2_R_R — 3 fields · 20 samples
and_base: 0x223a
var_mask: 0xfffff000
Bits
W
Tok
Extraction
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MOVM.16.MT88_P5_R_R — 2 fields · 16 samples
and_base: 0x0000000000000000000000010100523a
var_mask: 0x00000000000000000000001e1e1e0000
Bits
W
Tok
Extraction
[28:25]
4
t2
reg
[20:17]
4
t1
reg
MOVM.16.MT88_P_R_R — 3 fields · 20 samples
and_base: 0x23a
var_mask: 0xfffff000
Bits
W
Tok
Extraction
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
pred
MOVM.16.MT88_R_R — 2 fields · 10 samples
and_base: 0x723a
var_mask: 0xffff0000
Bits
W
Tok
Extraction
[31:24]
8
t1
reg
[23:16]
8
t0
reg
MOVM.U4TO8.M832
Matrix data move (SM120). MOVM.16.MT88 moves 16-bit data using MT88 (8×8 bit-packed) format, used to rearrange data before QMMA/HMMA. Bridges between register file layout and tensor core operand layout.
InsKey
Operands
Pipeline
Latency
MOVM.U4TO8.M832_R_R
R_R
MEMORY_SHARED
4 ~
MOVM.U4TO8.M832_R_R — 3 fields
and_base: 0x23a
var_mask: 0x1c0000000000000000000000fffff000
Bits
W
Tok
Extraction
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU
Multi-function unit. Evaluates transcendental approximations in ~8 cycles. Operations: .RCP (1/x), .SQRT (√x), .RSQ (1/√x), .SIN, .COS, .EX2 (2x), .LG2 (log2x), .TANH. Provides ~23 bits of accuracy (single-precision).
InsKey
Operands
Modifiers
Pipeline
Latency
MUFU_R_L
R_L
RSQ, COS, EX2, LG2, RCP, RCP64H, RSQ64H, SIN, SQRT
TEX_LOAD
8 ★
MUFU_R_R
R_R
COS, EX2, LG2, RCP, RCP64H, RSQ, RSQ64H, SIN, SQRT
TEX_LOAD
8 ★
MUFU_R_UR
R_UR
RCP, RSQ, COS, EX2, LG2, RCP64H, RSQ64H, SIN, SQRT
TEX_LOAD
8 ★
MUFU_R_L.RSQ — 1 fields · 150 samples
and_base: 0x1400ffc0000000007908
var_mask: 0x1c0000000000000000000000001f0000
Bits
W
Tok
Extraction
[20:16]
5
t1
reg
MUFU_R_L.COS — 4 fields · 1 samples
and_base: 0x00000000000000000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_L.EX2 — 4 fields · 1 samples
and_base: 0x00000000000008000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_L.LG2 — 4 fields · 1 samples
and_base: 0x0000000000000c000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_L.RCP — 4 fields · 8 samples
and_base: 0x00000000000010000000000000000308
var_mask: 0x1c00000000000000000000ff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_L.RCP64H — 4 fields · 1 samples
and_base: 0x00000000000018000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_L.RSQ64H — 4 fields · 1 samples
and_base: 0x0000000000001c000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_L.SIN — 4 fields · 1 samples
and_base: 0x00000000000004000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_L.SQRT — 4 fields · 1 samples
and_base: 0x00000000000020000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.COS — 4 fields · 1 samples
and_base: 0x00000000000000000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.EX2 — 4 fields · 1 samples
and_base: 0x00000000000008000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.LG2 — 4 fields · 1 samples
and_base: 0x0000000000000c000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.RCP — 4 fields · 8 samples
and_base: 0x00000000000010000000000000000308
var_mask: 0x1c00000000000000000000ff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.RCP64H — 4 fields · 1 samples
and_base: 0x00000000000018000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.RSQ — 4 fields · 1 samples
and_base: 0x00000000000014000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.RSQ64H — 4 fields · 1 samples
and_base: 0x0000000000001c000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.SIN — 4 fields · 1 samples
and_base: 0x00000000000004000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_R.SQRT — 4 fields · 1 samples
and_base: 0x00000000000020000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_UR.RCP — 3 fields · 3 samples
and_base: 0x000000000800100000000005005c7d08
var_mask: 0x1c00000000000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
MUFU_R_UR.RSQ — 1 fields · 150 samples
and_base: 0x1400ffc0000000007908
var_mask: 0x1c0000000000000000000000001f0000
Bits
W
Tok
Extraction
[20:16]
5
t1
reg
MUFU_R_UR.COS — 4 fields · 1 samples
and_base: 0x00000000000000000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_UR.EX2 — 4 fields · 1 samples
and_base: 0x00000000000008000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_UR.LG2 — 4 fields · 1 samples
and_base: 0x0000000000000c000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_UR.RCP64H — 4 fields · 1 samples
and_base: 0x00000000000018000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_UR.RSQ64H — 4 fields · 1 samples
and_base: 0x0000000000001c000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_UR.SIN — 4 fields · 1 samples
and_base: 0x00000000000004000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU_R_UR.SQRT — 4 fields · 1 samples
and_base: 0x00000000000020000000000000007308
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU.EX2
Multi-function unit. Evaluates transcendental approximations in ~8 cycles. Operations: .RCP (1/x), .SQRT (√x), .RSQ (1/√x), .SIN, .COS, .EX2 (2x), .LG2 (log2x), .TANH. Provides ~23 bits of accuracy (single-precision).
InsKey
Operands
Pipeline
Latency
MUFU.EX2_R_R
R_R
TEX_LOAD
8 ★
MUFU.EX2_R_R — 2 fields · 32 samples
and_base: 0x00000000000008000000000000007308
var_mask: 0x00000000000000000000001f003f0000
Bits
W
Tok
Extraction
[36:32]
5
t2
reg
[21:16]
6
t1
reg
MUFU.RCP
Multi-function unit. Evaluates transcendental approximations in ~8 cycles. Operations: .RCP (1/x), .SQRT (√x), .RSQ (1/√x), .SIN, .COS, .EX2 (2x), .LG2 (log2x), .TANH. Provides ~23 bits of accuracy (single-precision).
InsKey
Operands
Pipeline
Latency
MUFU.RCP_P_R_R
P_R_R
TEX_LOAD
8 ★
MUFU.RCP_R_R
R_R
TEX_LOAD
8 ★
MUFU.RCP_R_UR
R_UR
TEX_LOAD
8 ★
MUFU.RCP_P_R_R — 5 fields
and_base: 0x308
var_mask: 0x1c00000000000000c00000ff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[63:62]
2
t2
neg
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU.RCP_R_R — 5 fields
and_base: 0x308
var_mask: 0x1c00000000000000c00000ff00fff000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[63:62]
2
t2
neg
[39:32]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
MUFU.RCP_R_UR — 2 fields · 32 samples
and_base: 0x00000000000010000000000000007108
var_mask: 0x00000000080000000000007f007f0e00
Bits
W
Tok
Extraction
[38:32]
7
t2
ureg
[22:16]
7
t1
reg
MUFU.RCP64H
Multi-function unit. Evaluates transcendental approximations in ~8 cycles. Operations: .RCP (1/x), .SQRT (√x), .RSQ (1/√x), .SIN, .COS, .EX2 (2x), .LG2 (log2x), .TANH. Provides ~23 bits of accuracy (single-precision).
InsKey
Operands
Pipeline
Latency
MUFU.RCP64H_R_R
R_R
TEX_LOAD
8 ★
MUFU.RCP64H_R_R — 2 fields · 32 samples
and_base: 0x00000000000018000000000100017308
var_mask: 0x00000000000000000000003e003e0000
Bits
W
Tok
Extraction
[37:33]
5
t2
reg
[21:17]
5
t1
reg
MUFU.TANH
Multi-function unit. Evaluates transcendental approximations in ~8 cycles. Operations: .RCP (1/x), .SQRT (√x), .RSQ (1/√x), .SIN, .COS, .EX2 (2x), .LG2 (log2x), .TANH. Provides ~23 bits of accuracy (single-precision).
InsKey
Operands
Pipeline
Latency
MUFU.TANH_R_R
R_R
TEX_LOAD
8 ★
MUFU.TANH_R_R — 3 fields · 32 samples
and_base: 0x00000000000024000000000000000308
var_mask: 0x00000000000000000000001f001f7000
Bits
W
Tok
Extraction
[36:32]
5
t2
reg
[20:16]
5
t1
reg
[14:12]
3
t0
guard
NANOSLEEP
Insert a ~N-nanosecond delay in the warp. Useful for reducing memory contention.
InsKey
Operands
Pipeline
Latency
NANOSLEEP_II
II
TEX_LOAD
30 ~
NANOSLEEP_R
R
TEX_LOAD
30 ~
NANOSLEEP_II — 3 fields
and_base: 0x95d
var_mask: 0x1c00000007800000ffffffff0000f000
Bits
W
Tok
Extraction
[90:87]
4
t1
imm
[63:32]
32
t1
imm
[15:12]
4
t0
guard
NANOSLEEP_R — 3 fields
and_base: 0x3800000000000000000035d
var_mask: 0xfc00000000000000000000ff0000f000
Bits
W
Tok
Extraction
[123]
1
t1
reuse
[39:32]
8
t1
reg
[15:12]
4
t0
guard
NOP
No operation.
InsKey
Operands
Pipeline
Latency
NOP
CTRL_FLOW
0 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
NOP_?
?
CTRL_FLOW
0 ~
OMMA.SF.16864.F32.E2M1.E2M1.E8
Operand Microscaling MMA. New opcode family (0x47F). Block-scaled FP4 (E2M1) matrix multiply-accumulate. Shape: 16×8×64 (K=64 for FP4: 64 elements × 4 bits = 256 bits). Two variants: .E8 (UE8M0 scale, OCP-compliant MXF4) and .UE4M3.4X (NVF4, NVIDIA-proprietary with finer 4× scaling). Operands: Rd, Ra, Rb, Rc (accumulator), R_SFA, R_SFB (scale factors), UR (selector). PTX: kind::mxf4.block_scale / kind::mxf4nvf4.block_scale. Requires compute_120f (CUDA 13.0+). Discovered 2026-03-11 via ptxas 13.1.
3 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
P2R_R_R_R_II_II_?
R_R_R_II_II_?
INT_ARITH
4 ~
P2R_R_R_R_II_II_II_?
R_R_R_II_II_II_?
INT_ARITH
4 ~
P2R_R_R_R_II_II_II_II_?
R_R_R_II_II_II_II_?
INT_ARITH
4 ~
P2R_R_R_R_II_II_? — 2 fields · 10 samples
and_base: 0x000000000000000000000000ff007803
var_mask: 0x00000000000000000000003f001f0000
Bits
W
Tok
Extraction
[37:32]
6
t4
imm
[20:16]
5
t1
reg
P2R_R_R_R_II_II_II_? — 2 fields · 7 samples
and_base: 0x000000000000000000000000ff007803
var_mask: 0x00000000000000000000003f000f0000
Bits
W
Tok
Extraction
[37:32]
6
t4
imm
[19:16]
4
t1
reg
P2R_R_R_R_II_II_II_II_? — 2 fields · 3 samples
and_base: 0x000000000000000000000000ff007803
var_mask: 0x00000000000000000000003f001e0000
Bits
W
Tok
Extraction
[37:32]
6
t4
imm
[20:17]
4
t1
reg
P2R_P_R_R_R_R — 11 fields
and_base: 0x27a
var_mask: 0x1c000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
reuse
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
P2R_R_L_R_II — 1 fields · 6 samples
and_base: 0x000000000000000000000001ff007803
var_mask: 0x1c000000000000000000000000ff0000
Bits
W
Tok
Extraction
[23:16]
8
t1
reg
P2R_R_R_R_II — 2 fields · 32 samples
and_base: 0x000000000000000000000000ff007803
var_mask: 0x00000000000000000000007f00ff0000
Bits
W
Tok
Extraction
[38:32]
7
t4
imm
[23:16]
8
t1
reg
P2R_R_R_R_II_II — 2 fields · 28 samples
and_base: 0x000000000000000000000000ff007803
var_mask: 0x00000000000000000000007f003f0000
Bits
W
Tok
Extraction
[38:32]
7
t4
imm
[21:16]
6
t1
reg
P2R.B1
Pack predicate register values into GPR bits.
InsKey
Operands
Pipeline
Latency
P2R.B1_R_R_R_II
R_R_R_II
INT_ARITH
4 ~
P2R.B1_R_R_R_II — 2 fields · 32 samples
and_base: 0x00000000000010000000000fc8c87803
var_mask: 0x00000000000000000000000006060000
Bits
W
Tok
Extraction
[26:25]
2
t3
reg
[18:17]
2
t1
reg
PLOP3
3-input predicate logical operation.
InsKey
Operands
Modifiers
Pipeline
Latency
PLOP3_P_P_P_P_P_II_II
P_P_P_P_P_II_II
LUT
INT_ARITH
4 ~
PLOP3_P_P_P_P_UP_II_II
P_P_P_P_UP_II_II
LUT
INT_ARITH
4 ~
PLOP3_P_P_P_P_P_II_II.LUT — 12 fields
and_base: 0x81c
var_mask: 0x1c00000007fffff70000000000fff000
Bits
W
Tok
Extraction
[90]
1
t3
neg
[89:87]
3
t3
pred
[86:84]
3
t2
pred
[83:81]
3
t1
pred
[80]
1
t4
neg
[79:77]
3
t4
pred
[76:72]
5
t6
imm
[71]
1
t5
neg
[70:68]
3
t5
pred
[66:64]
3
t6
imm
[23:16]
8
t7
imm
[15:12]
4
t0
guard
PLOP3_P_P_P_P_UP_II_II.LUT — 7 fields
and_base: 0x0000000000700008000000000000081c
var_mask: 0x1ffffe00038eff700000000000fff000
Bits
W
Tok
Extraction
[89:87]
3
t3
pred
[83:81]
3
t1
pred
[79:77]
3
t4
pred
[76:72]
5
t6
imm_shr3
[70:68]
3
t5
pred
[23:16]
8
t7
imm
[15:12]
4
t0
guard
PLOP3.LUT
3-input predicate logical operation.
InsKey
Operands
Pipeline
Latency
PLOP3.LUT_P1_P_P_P_P_P_II_II
P1_P_P_P_P_P_II_II
INT_ARITH
4 ~
PLOP3.LUT_P_P_P_P_P_II_II
P_P_P_P_P_II_II
INT_ARITH
4 ~
PLOP3.LUT_P_P_P_P_UP_II_II
P_P_P_P_UP_II_II
INT_ARITH
4 ~
PLOP3.LUT_P1_P_P_P_P_P_II_II — 13 fields
and_base: 0x81c
var_mask: 0x7fffff70000000000fff080
Bits
W
Tok
Extraction
[90]
1
t3
neg
[89:87]
3
t3
pred
[86:84]
3
t2
pred
[83:81]
3
t1
pred
[80]
1
t4
neg
[79:77]
3
t4
pred
[76:72]
5
t6
imm
[71]
1
t5
neg
[70:68]
3
t5
pred
[66:64]
3
t6
imm
[23:16]
8
t7
imm
[15:12]
4
t0
guard
[7]
1
t0
guard
PLOP3.LUT_P_P_P_P_P_II_II — 12 fields
and_base: 0x81c
var_mask: 0x1c00000007fffff70000000000fff000
Bits
W
Tok
Extraction
[90]
1
t3
neg
[89:87]
3
t3
pred
[86:84]
3
t2
pred
[83:81]
3
t1
pred
[80]
1
t4
neg
[79:77]
3
t4
pred
[76:72]
5
t6
imm
[71]
1
t5
neg
[70:68]
3
t5
pred
[66:64]
3
t6
imm
[23:16]
8
t7
imm
[15:12]
4
t0
guard
PLOP3.LUT_P_P_P_P_UP_II_II — 12 fields
and_base: 0x8000000000000081c
var_mask: 0x1c00000007fffff70000000000fff000
Bits
W
Tok
Extraction
[90]
1
t3
neg
[89:87]
3
t3
pred
[86:84]
3
t2
pred
[83:81]
3
t1
pred
[80]
1
t4
neg
[79:77]
3
t4
pred
[76:72]
5
t6
imm
[71]
1
t5
neg
[70:68]
3
t5
upred
[66:64]
3
t6
imm
[23:16]
8
t7
imm
[15:12]
4
t0
guard
POPC
Population count (Hamming weight).
InsKey
Operands
Pipeline
Latency
POPC_R_R
R_R
INT_ARITH
8 ★
POPC_R_UR
R_UR
INT_ARITH
8 ★
POPC_R_UR_UR
R_UR_UR
INT_ARITH
8 ★
POPC_R_R — 3 fields · 110 samples
and_base: 0x00000000000000000000000000007309
var_mask: 0x1c00000000000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
reg
[23:16]
8
t1
reg
POPC_R_UR — 3 fields · 77 samples
and_base: 0x00000000080000000000000400017d09
var_mask: 0x1c00000000000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[39:32]
8
t2
ureg
[23:16]
8
t1
reg
POPC_R_UR_UR — 2 fields · 5 samples
and_base: 0x00000000080000000000000000017d09
var_mask: 0x00000000000000000000001c000e0000
Bits
W
Tok
Extraction
[36:34]
3
t2
ureg
[19:17]
3
t1
reg
PREEXIT
InsKey
Operands
Pipeline
Latency
PREEXIT
CTRL_FLOW
0 ~
PREEXIT_P
P
CTRL_FLOW
0 ~
PREEXIT — 1 fields
and_base: 0x82d
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
PREEXIT_P — 1 fields
and_base: 0x82d
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
PRMT
Byte permute. Selects and rearranges 4 bytes from a pair of 32-bit sources (Ra:Rb as 8-byte pool) according to a 16-bit control word. Each nibble of the control selects one byte. Used for format conversion and byte-level data shuffles.
InsKey
Operands
Pipeline
Latency
PRMT_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
PRMT_R_R_II_R_R
R_R_II_R_R
INT_ARITH
4 ★
4 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
PRMT_R_R_II_R_II_?
R_R_II_R_II_?
INT_ARITH
4 ★
PRMT_R_R_II_R_II_II_?
R_R_II_R_II_II_?
INT_ARITH
4 ★
PRMT_R_R_II_R_II_II_II_?
R_R_II_R_II_II_II_?
INT_ARITH
4 ★
PRMT_R_R_II_R_II_II_II_II_?
R_R_II_R_II_II_II_II_?
INT_ARITH
4 ★
PRMT_R_R_II_R_II_II_? — 4 fields · 32 samples
and_base: 0x00000000000000010000760000017816
var_mask: 0x000000000000001e0000003eff1e0000
Bits
W
Tok
Extraction
[68:65]
4
t4
reg
[37:33]
5
t3
imm
[31:24]
8
t2
imm
[20:17]
4
t1
reg
PRMT_R_R_II_R_II_II_II_? — 4 fields · 15 samples
and_base: 0x00000000000000000000760018007816
var_mask: 0x000000000000001f0000003e071f0000
Bits
W
Tok
Extraction
[68:64]
5
t4
reg
[37:33]
5
t3
imm
[26:24]
3
t2
reg
[20:16]
5
t1
reg
PRMT_R_R_II_R — 7 fields · 367 samples
and_base: 0x00000000000000000000000000000816
var_mask: 0x1c000000000000ff0000ff37fffff000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
PRMT_R_R_II_R_R — 3 fields · 32 samples
and_base: 0x000000000000000000004010ff007816
var_mask: 0x00000000000000ff00003e00003f0000
Bits
W
Tok
Extraction
[71:64]
8
t4
reg
[45:41]
5
t3
imm
[21:16]
6
t1
reg
QMMA.16816.F16.E2M3.E2M3
Quantized matrix multiply-accumulate. SM120-exclusive (RTX 5090). Performs FP8/FP6 warp-group MMA in a single instruction. Opcode 0x27A. Supported types: E4M3 (FP8), E5M2 (FP8), E2M3 (FP6). Shapes: 16×8×16, 16×8×32, 16×8×64 (K=64). SP variants (.SP) exploit 2:4 structured sparsity for ~1.6× throughput. SF variants (.SF, opcode 0x47A) add per-block UE8M0 scale factors for microscaling (PTX: kind::mxf8f6f4.block_scale, requires compute_120f / CUDA 13+). SF.SP variants combine block-scaling with 2:4 sparsity. Undocumented modifier bits: negate accumulator (shape bit[0]), exponent scale A/B (shape bits[6:7]), negate B (lo[63]).
InsKey
Operands
Pipeline
Latency
QMMA.16816.F16.E2M3.E2M3_P_R_R_R_R
P_R_R_R_R
HMMA
16 ~
QMMA.16816.F16.E2M3.E2M3_R_R_R_R
R_R_R_R
HMMA
16 ~
QMMA.16816.F16.E2M3.E2M3_P_R_R_R_R — 8 fields
and_base: 0x280400000000000000027a
var_mask: 0x8000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
QMMA.16816.F16.E2M3.E2M3_R_R_R_R — 8 fields
and_base: 0x280400000000000000027a
var_mask: 0x8000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
QMMA.16816.F16.E2M3.E4M3
Quantized matrix multiply-accumulate. SM120-exclusive (RTX 5090). Performs FP8/FP6 warp-group MMA in a single instruction. Opcode 0x27A. Supported types: E4M3 (FP8), E5M2 (FP8), E2M3 (FP6). Shapes: 16×8×16, 16×8×32, 16×8×64 (K=64). SP variants (.SP) exploit 2:4 structured sparsity for ~1.6× throughput. SF variants (.SF, opcode 0x47A) add per-block UE8M0 scale factors for microscaling (PTX: kind::mxf8f6f4.block_scale, requires compute_120f / CUDA 13+). SF.SP variants combine block-scaling with 2:4 sparsity. Undocumented modifier bits: negate accumulator (shape bit[0]), exponent scale A/B (shape bits[6:7]), negate B (lo[63]).
InsKey
Operands
Pipeline
Latency
QMMA.16816.F16.E2M3.E4M3_P_R_R_R_R
P_R_R_R_R
HMMA
16 ~
QMMA.16816.F16.E2M3.E4M3_R_R_R_R
R_R_R_R
HMMA
16 ~
QMMA.16816.F16.E2M3.E4M3_P_R_R_R_R — 8 fields
and_base: 0x80400000000000000027a
var_mask: 0x8000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
QMMA.16816.F16.E2M3.E4M3_R_R_R_R — 8 fields
and_base: 0x80400000000000000027a
var_mask: 0x1c000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
QMMA.16816.F16.E2M3.E5M2
Quantized matrix multiply-accumulate. SM120-exclusive (RTX 5090). Performs FP8/FP6 warp-group MMA in a single instruction. Opcode 0x27A. Supported types: E4M3 (FP8), E5M2 (FP8), E2M3 (FP6). Shapes: 16×8×16, 16×8×32, 16×8×64 (K=64). SP variants (.SP) exploit 2:4 structured sparsity for ~1.6× throughput. SF variants (.SF, opcode 0x47A) add per-block UE8M0 scale factors for microscaling (PTX: kind::mxf8f6f4.block_scale, requires compute_120f / CUDA 13+). SF.SP variants combine block-scaling with 2:4 sparsity. Undocumented modifier bits: negate accumulator (shape bit[0]), exponent scale A/B (shape bits[6:7]), negate B (lo[63]).
InsKey
Operands
Pipeline
Latency
QMMA.16816.F16.E2M3.E5M2_P_R_R_R_R
P_R_R_R_R
HMMA
16 ~
QMMA.16816.F16.E2M3.E5M2_R_R_R_R
R_R_R_R
HMMA
16 ~
QMMA.16816.F16.E2M3.E5M2_P_R_R_R_R — 8 fields
and_base: 0x88400000000000000027a
var_mask: 0x8000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
QMMA.16816.F16.E2M3.E5M2_R_R_R_R — 8 fields
and_base: 0x88400000000000000027a
var_mask: 0x8000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
QMMA.16816.F16.E4M3.E2M3
Quantized matrix multiply-accumulate. SM120-exclusive (RTX 5090). Performs FP8/FP6 warp-group MMA in a single instruction. Opcode 0x27A. Supported types: E4M3 (FP8), E5M2 (FP8), E2M3 (FP6). Shapes: 16×8×16, 16×8×32, 16×8×64 (K=64). SP variants (.SP) exploit 2:4 structured sparsity for ~1.6× throughput. SF variants (.SF, opcode 0x47A) add per-block UE8M0 scale factors for microscaling (PTX: kind::mxf8f6f4.block_scale, requires compute_120f / CUDA 13+). SF.SP variants combine block-scaling with 2:4 sparsity. Undocumented modifier bits: negate accumulator (shape bit[0]), exponent scale A/B (shape bits[6:7]), negate B (lo[63]).
InsKey
Operands
Pipeline
Latency
QMMA.16816.F16.E4M3.E2M3_P_R_R_R_R
P_R_R_R_R
HMMA
16 ~
QMMA.16816.F16.E4M3.E2M3_R_R_R_R
R_R_R_R
HMMA
16 ~
QMMA.16816.F16.E4M3.E2M3_P_R_R_R_R — 8 fields
and_base: 0x200400000000000000027a
var_mask: 0x8000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
QMMA.16816.F16.E4M3.E2M3_R_R_R_R — 8 fields
and_base: 0x200400000000000000027a
var_mask: 0x1c000000000001ff800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[72]
1
t2
neg
[71:64]
8
t4
reg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
QMMA.16816.F16.E4M3.E4M3
Quantized matrix multiply-accumulate. SM120-exclusive (RTX 5090). Performs FP8/FP6 warp-group MMA in a single instruction. Opcode 0x27A. Supported types: E4M3 (FP8), E5M2 (FP8), E2M3 (FP6). Shapes: 16×8×16, 16×8×32, 16×8×64 (K=64). SP variants (.SP) exploit 2:4 structured sparsity for ~1.6× throughput. SF variants (.SF, opcode 0x47A) add per-block UE8M0 scale factors for microscaling (PTX: kind::mxf8f6f4.block_scale, requires compute_120f / CUDA 13+). SF.SP variants combine block-scaling with 2:4 sparsity. Undocumented modifier bits: negate accumulator (shape bit[0]), exponent scale A/B (shape bits[6:7]), negate B (lo[63]).
Reduction on global memory (fire-and-forget atomic).
InsKey
Operands
Pipeline
Latency
REDG.E.OR.STRONG.GPU_P_dARI_R
P_dARI_R
MEMORY
0 ~
REDG.E.OR.STRONG.GPU_P_dARI_R — 9 fields
and_base: 0xc020000000000000000098e
var_mask: 0x1c000000000000ffffffffffff00f040
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t1
ureg
[63:40]
24
t1
imm
[39:32]
8
t2
reg
[31:24]
8
t1
reg
[15:12]
4
t0
guard
[6]
1
t0
guard
REDUX
Warp-level reduction to a uniform register. Reduces a value across all active threads in a warp using an operation (AND, OR, XOR, ADD, MIN, MAX) and writes the result to a UR. Faster than a shared-memory reduction for small reductions.
InsKey
Operands
Modifiers
Pipeline
Latency
REDUX_UR_R
UR_R
SUM
WARP_SYNC
4 ~
REDUX_UR_R.SUM — 3 fields · 10 samples
and_base: 0x000000000000c00000000000000073c4
var_mask: 0x1c0000000000000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
reg
[23:16]
8
t1
ureg
REDUX.MAX.S32
Warp-level reduction to a uniform register. Reduces a value across all active threads in a warp using an operation (AND, OR, XOR, ADD, MIN, MAX) and writes the result to a UR. Faster than a shared-memory reduction for small reductions.
InsKey
Operands
Pipeline
Latency
REDUX.MAX.S32_UR_R
UR_R
WARP_SYNC
4 ~
REDUX.MAX.S32_UR_R — 4 fields
and_base: 0x3c4
var_mask: 0x1c0000000000000000000000fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
reg
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
REDUX.MIN
Warp-level reduction to a uniform register. Reduces a value across all active threads in a warp using an operation (AND, OR, XOR, ADD, MIN, MAX) and writes the result to a UR. Faster than a shared-memory reduction for small reductions.
InsKey
Operands
Pipeline
Latency
REDUX.MIN_UR_R
UR_R
WARP_SYNC
4 ~
REDUX.MIN_UR_R — 1 fields · 32 samples
and_base: 0x000000000001000000000000000473c4
var_mask: 0x000000000000000000000000ff000000
Bits
W
Tok
Extraction
[31:24]
8
t2
reg
REDUX.MIN.S32
Warp-level reduction to a uniform register. Reduces a value across all active threads in a warp using an operation (AND, OR, XOR, ADD, MIN, MAX) and writes the result to a UR. Faster than a shared-memory reduction for small reductions.
InsKey
Operands
Pipeline
Latency
REDUX.MIN.S32_UR_R
UR_R
WARP_SYNC
4 ~
REDUX.MIN.S32_UR_R — 4 fields
and_base: 0x3c4
var_mask: 0x1c0000000000000000000000fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
reg
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
REDUX.OR
Warp-level reduction to a uniform register. Reduces a value across all active threads in a warp using an operation (AND, OR, XOR, ADD, MIN, MAX) and writes the result to a UR. Faster than a shared-memory reduction for small reductions.
InsKey
Operands
Pipeline
Latency
REDUX.OR_UR_R
UR_R
WARP_SYNC
4 ~
REDUX.OR_UR_R — 4 fields
and_base: 0x3c4
var_mask: 0x1c0000000000000000000000fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
reg
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
REDUX.SUM
Warp-level reduction to a uniform register. Reduces a value across all active threads in a warp using an operation (AND, OR, XOR, ADD, MIN, MAX) and writes the result to a UR. Faster than a shared-memory reduction for small reductions.
InsKey
Operands
Pipeline
Latency
REDUX.SUM_UR_R
UR_R
WARP_SYNC
4 ~
REDUX.SUM_UR_R — 4 fields
and_base: 0x3c4
var_mask: 0x1c0000000000000000000000fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
reg
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
REDUX.SUM.S32
Warp-level reduction to a uniform register. Reduces a value across all active threads in a warp using an operation (AND, OR, XOR, ADD, MIN, MAX) and writes the result to a UR. Faster than a shared-memory reduction for small reductions.
InsKey
Operands
Pipeline
Latency
REDUX.SUM.S32_UR_R
UR_R
WARP_SYNC
4 ~
REDUX.SUM.S32_UR_R — 4 fields
and_base: 0x3c4
var_mask: 0x1c0000000000000000000000fffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
reg
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
RET
Return from subroutine.
InsKey
Operands
Modifiers
Pipeline
Latency
RET_L
L
ABS,NODEC, NODEC,REL
CTRL_FLOW
0 ~
RET_L.ABS,NODEC — 4 fields · 7 samples
and_base: 0x0000000003e000000000000000007950
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[81:34]
48
t0
[31:24]
8
t1
reg
[23:16]
8
t0
RET_L.NODEC,REL — 4 fields · 7 samples
and_base: 0x0000000003c3ffffffffffe000007950
var_mask: 0x1c000000000000000000001cfffc0000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[81:34]
48
t0
[31:24]
8
t1
reg
[23:16]
8
t0
RET.ABS.NODEC
Return from subroutine.
InsKey
Operands
Pipeline
Latency
RET.ABS.NODEC_?
?
CTRL_FLOW
0 ~
RET.REL.NODEC
Return from subroutine.
InsKey
Operands
Pipeline
Latency
RET.REL.NODEC_II
II
CTRL_FLOW
0 ~
RET.REL.NODEC_R
R
CTRL_FLOW
0 ~
RET.REL.NODEC_II — 2 fields · 32 samples
and_base: 0x0000000003c3fffffffffe0000007950
var_mask: 0x0000000000000000000001fffffc0000
Bits
W
Tok
Extraction
[30:25]
6
t1
reg
[40:18]
23
t1
imm
RET.REL.NODEC_R — 6 fields
and_base: 0x950
var_mask: 0x1c0000000783fffffffffffcfffff000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[90:87]
4
t1
imm
[81:34]
48
t1
imm
[31:24]
8
t1
reg
[23:16]
8
t1
imm
[15:12]
4
t0
guard
S2R
Read special register. Provides access to per-thread hardware state: SR_TID.X/Y/Z (thread index within block), SR_CTAID.X/Y/Z (block index within grid), SR_CLOCK (clock counter), SR_LANEID (warp lane), etc. ~20 cycle latency; uses ADU pipe.
InsKey
Operands
Pipeline
Latency
S2R_P0_R_L
P0_R_L
SPECIAL
4 ★
S2R_R_II
R_II
SPECIAL
4 ★
S2R_R_L
R_L
SPECIAL
4 ★
S2R_R_L_II
R_L_II
SPECIAL
4 ★
3 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
S2R_R_L_II_?
R_L_II_?
SPECIAL
4 ★
S2R_R_L_II_II_?
R_L_II_II_?
SPECIAL
4 ★
S2R_R_L_II_II_II_?
R_L_II_II_II_?
SPECIAL
4 ★
S2R_R_L_II_? — 2 fields · 32 samples
and_base: 0x00000000000000000000000000007919
var_mask: 0x000000000000ff0000000000007f0000
Bits
W
Tok
Extraction
[79:72]
8
t2
imm
[22:16]
7
t1
reg
S2R_R_L_II_II_? — 2 fields · 31 samples
and_base: 0x00000000000000000000000000007919
var_mask: 0x000000000000ff0000000000003f0000
Bits
W
Tok
Extraction
[79:72]
8
t2
imm
[21:16]
6
t1
reg
S2R_P0_R_L — 4 fields
and_base: 0x80000000000000000919
var_mask: 0xb000000000000fff000
Bits
W
Tok
Extraction
[75]
1
t2
imm
[73:72]
2
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
S2R_R_II — 3 fields
and_base: 0x919
var_mask: 0x1c00000000007f000000000000fff000
Bits
W
Tok
Extraction
[78:72]
7
t2
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
S2R_R_L — 4 fields · 210 samples
and_base: 0x00000000000000000000000000000919
var_mask: 0x1c0000000000bf000000000000fff000
Bits
W
Tok
Extraction
[79]
1
t2
sysreg_hi1
[78:72]
7
t2
sysreg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
S2R_R_L_II — 2 fields · 32 samples
and_base: 0x00000000000000000000000000007919
var_mask: 0x000000000000ff0000000000003f0000
Bits
W
Tok
Extraction
[79:72]
8
t2
imm
[21:16]
6
t1
reg
S2UR
Special register to uniform register.
InsKey
Operands
Pipeline
Latency
S2UR_UR_II
UR_II
SPECIAL
20 ~
S2UR_UR_L
UR_L
SPECIAL
20 ~
S2UR_UR_II — 4 fields
and_base: 0x800000000000000009c3
var_mask: 0x1c00000000000b000000000000fff000
Bits
W
Tok
Extraction
[75]
1
t2
imm
[73:72]
2
t2
imm
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
S2UR_UR_L — 5 fields · 19 samples
and_base: 0x000000000000000000000000000079c3
var_mask: 0x1c0000000000ad000000000000ff0000
Bits
W
Tok
Extraction
[79:76]
4
t2
sysreg_hi4
[75]
1
t2
sysreg_hi1
[74]
1
t2
sysreg
[73:72]
2
t2
sysreg
[23:16]
8
t1
ureg
SEL
Conditional select. Rd = Pd ? Ra : Rb.
InsKey
Operands
Modifiers
Pipeline
Latency
SEL_P_R_R_II_P
P_R_R_II_P
—
INT_ARITH
4 ★
SEL_R_R_II_P
R_R_II_P
64
INT_ARITH
4 ★
SEL_R_R_R_P
R_R_R_P
64
INT_ARITH
4 ★
SEL_R_R_R_P_P
R_R_R_P_P
—
INT_ARITH
4 ★
SEL_R_R_UR_P
R_R_UR_P
64
INT_ARITH
4 ★
5 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
SEL_R_R_II_P_?
R_R_II_P_?
INT_ARITH
4 ★
SEL_R_R_R_P_II_?
R_R_R_P_II_?
INT_ARITH
4 ★
SEL_R_R_R_P_II_II_?
R_R_R_P_II_II_?
INT_ARITH
4 ★
SEL_R_R_R_P_II_II_II_?
R_R_R_P_II_II_II_?
INT_ARITH
4 ★
SEL_R_R_R_P_II_II_II_II_?
R_R_R_P_II_II_II_II_?
INT_ARITH
4 ★
SEL_R_R_R_P_II_? — 4 fields · 2 samples
and_base: 0x00000000000000000000000100017207
var_mask: 0x0000000003800000000000fe1e1e0000
Bits
W
Tok
Extraction
[89:87]
3
t4
pred
[39:33]
7
t3
imm
[28:25]
4
t2
reg
[20:17]
4
t1
reg
SEL_R_R_R_P_II_II_? — 2 fields · 2 samples
and_base: 0x0000000000000000000000ff020b7207
var_mask: 0x0000000001800000000000000c000000
Bits
W
Tok
Extraction
[88:87]
2
t4
pred
[27:26]
2
t2
reg
SEL_R_R_R_P_II_II_II_? — 8 fields · 1 samples
and_base: 0x00000000000000000000000000000207
var_mask: 0x1c00000007800000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[90]
1
t4
inv
[89:87]
3
t4
pred
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
SEL_R_R_R_P_II_II_II_II_? — 8 fields · 1 samples
and_base: 0x00000000000000000000000000000207
var_mask: 0x1c00000007800000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[90]
1
t4
inv
[89:87]
3
t4
pred
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
SEL_P_R_R_II_P — 6 fields
and_base: 0xff000807
var_mask: 0x1c00000007800000ffffffff00fff000
Bits
W
Tok
Extraction
[122]
1
t2
neg
[90]
1
t4
neg
[89:87]
3
t4
pred
[63:32]
32
t3
imm
[23:16]
8
t1
reg
[15:12]
4
t0
guard
SEL_R_R_II_P — 7 fields · 390 samples
and_base: 0x00000000000000000000000000000807
var_mask: 0x1c00000007800000fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[90]
1
t4
inv
[89:87]
3
t4
pred
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
SEL_R_R_II_P.64 — 6 fields · 647 samples
and_base: 0x00000000000000000000000104007407
var_mask: 0x1c00000003800001fffffffeffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[89:87]
3
t4
pred
[64]
1
t3
imm_shr3
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
SEL_R_R_R_P — 8 fields · 122 samples
and_base: 0x00000000000000000000000000001207
var_mask: 0x1c00000007800000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[90]
1
t4
inv
[89:87]
3
t4
pred
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
SEL_R_R_R_P.64 — 8 fields
and_base: 0x00000000000000000000000000000607
var_mask: 0x1ffffe0007800000fffffffffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[90]
1
t4
inv
[89:87]
3
t4
pred
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
SEL_R_R_R_P_P — 4 fields · 8 samples
and_base: 0x00000000000000000000000100017207
var_mask: 0x0000000003800000000000fe1e1e0000
Bits
W
Tok
Extraction
[89:87]
3
t4
pred
[39:33]
7
t3
reg
[28:25]
4
t2
reg
[20:17]
4
t1
reg
SEL_R_R_UR_P — 6 fields · 52 samples
and_base: 0xc0000000000000000007c07
var_mask: 0x1c000000018000000000000f3f3f0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[88:87]
2
t4
imm
[35:32]
4
t3
ureg
[29:24]
6
t2
reg
[21:16]
6
t1
reg
SEL_R_R_UR_P.64 — 7 fields · 647 samples
and_base: 0x00000000000000000000000104007407
var_mask: 0x1c00000003800001ffffffffffff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[89:87]
3
t4
pred
[64]
1
t3
imm_shr3
[63:32]
32
t3
ureg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
SEL.64
Conditional select. Rd = Pd ? Ra : Rb.
InsKey
Operands
Pipeline
Latency
SEL.64_R_R_II_P
R_R_II_P
INT_ARITH
4 ★
SEL.64_R_R_R_P
R_R_R_P
INT_ARITH
4 ★
SEL.64_R_R_II_P — 2 fields · 32 samples
and_base: 0x00000000040000000000000100007407
var_mask: 0x0000000000000000000000003e3e0000
Bits
W
Tok
Extraction
[29:25]
5
t2
reg
[21:17]
5
t1
reg
SEL.64_R_R_R_P — 11 fields
and_base: 0x7
var_mask: 0x1c00000007800000000000fffffff200
Bits
W
Tok
Extraction
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[90]
1
t4
neg
[89:87]
3
t4
pred
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
[9]
1
t3
imm
SGXT
Sign extend. Extends a value from a specified bit width to 32 bits.
InsKey
Operands
Pipeline
Latency
SGXT_R_R_II
R_R_II
INT_ARITH
4 ★
SGXT_R_R_II — 3 fields · 2 samples
and_base: 0x0000000000000200000000080004781a
var_mask: 0x1c0000000000000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[31:24]
8
t2
reg
[23:16]
8
t1
reg
SHF
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.L.U32_P0_R_R_II_R
P0_R_R_II_R
INT_ARITH
4 ★
SHF.L.U32_R_R_II_II
R_R_II_II
INT_ARITH
4 ★
SHF.L.U32_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.L.U32_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
SHF.L.U32_R_R_UR_UR
R_R_UR_UR
INT_ARITH
4 ★
4 partial encodings — operand types not fully identified
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.L.U32.HI_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.L.U32.HI_R_R_II_R — 4 fields · 27 samples
and_base: 0x00000000000106000000001000007819
var_mask: 0x000000000000007f0000000f7f7f0000
Bits
W
Tok
Extraction
[70:64]
7
t4
reg
[35:32]
4
t3
imm
[30:24]
7
t2
reg
[22:16]
7
t1
reg
SHF.L.U64.HI
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.L.U64.HI_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.L.U64.HI_R_R_II_R_R
R_R_II_R_R
INT_ARITH
4 ★
2 partial encodings — operand types not fully identified
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.L.W.U32_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
SHF.L.W.U32_R_R_R_R — 3 fields · 24 samples
and_base: 0x0000000000000eff0000000000017219
var_mask: 0x00000000000000000000003f3f3e0000
Bits
W
Tok
Extraction
[37:32]
6
t3
reg
[29:24]
6
t2
reg
[21:17]
5
t1
reg
SHF.L.W.U32.HI
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.L.W.U32.HI_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.L.W.U32.HI_R_R_R_II
R_R_R_II
INT_ARITH
4 ★
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
SHF.L.W.U32.HI_R_R_II_R_?
R_R_II_R_?
INT_ARITH
4 ★
SHF.L.W.U32.HI_R_R_II_R_? — 1 fields · 5 samples
and_base: 0x0000000000010e080000001a08017819
var_mask: 0x000000000000000000000000003e0000
Bits
W
Tok
Extraction
[21:17]
5
t1
reg
SHF.L.W.U32.HI_R_R_II_R — 4 fields · 32 samples
and_base: 0x0000000000010e000000001000007819
var_mask: 0x000000000000003f0000000f3f3f0000
Bits
W
Tok
Extraction
[69:64]
6
t4
reg
[35:32]
4
t3
imm
[29:24]
6
t2
reg
[21:16]
6
t1
reg
SHF.L.W.U32.HI_R_R_R_II — 4 fields · 32 samples
and_base: 0x0000000000010e00fffffffe00000419
var_mask: 0x000000000000001f000000001f1f7000
Bits
W
Tok
Extraction
[68:64]
5
t3
reg
[28:24]
5
t2
reg
[20:16]
5
t1
reg
[14:12]
3
t0
guard
SHF.R.S32.HI
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.R.S32.HI_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.R.S32.HI_R_R_II_R_R
R_R_II_R_R
INT_ARITH
4 ★
SHF.R.S32.HI_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
3 partial encodings — operand types not fully identified
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.R.S64_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.R.S64_R_R_II_R — 3 fields · 32 samples
and_base: 0x00000000000010010000000300007819
var_mask: 0x000000000000003e000000003e3e0000
Bits
W
Tok
Extraction
[69:65]
5
t4
reg
[29:25]
5
t2
reg
[21:17]
5
t1
reg
SHF.R.U32.HI
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.R.U32.HI_P_R_R_II_R
P_R_R_II_R
INT_ARITH
4 ★
SHF.R.U32.HI_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.R.U32.HI_R_R_II_R_R
R_R_II_R_R
INT_ARITH
4 ★
SHF.R.U32.HI_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
SHF.R.U32.HI_R_R_UR_R
R_R_UR_R
INT_ARITH
4 ★
2 partial encodings — operand types not fully identified
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.R.U64_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.R.U64_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
SHF.R.U64_R_R_UR_R
R_R_UR_R
INT_ARITH
4 ★
SHF.R.U64_R_R_II_R — 7 fields
and_base: 0x819
var_mask: 0x1c000000000000fffffffffffffff000
Bits
W
Tok
Extraction
[124]
1
t4
reuse
[122]
1
t2
reuse
[71:64]
8
t4
reg
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
SHF.R.U64_R_R_R_R — 4 fields · 21 samples
and_base: 0x00000000000012010000000100007219
var_mask: 0x000000000000007e0000007e7e7f0000
Bits
W
Tok
Extraction
[70:65]
6
t4
reg
[38:33]
6
t3
reg
[30:25]
6
t2
reg
[22:16]
7
t1
reg
SHF.R.U64_R_R_UR_R — 4 fields · 32 samples
and_base: 0x00000000080012000000000000007c19
var_mask: 0x000000000000003f000000183f3e0000
Bits
W
Tok
Extraction
[69:64]
6
t4
reg
[36:35]
2
t3
ureg
[29:24]
6
t2
reg
[21:17]
5
t1
reg
SHF.R.W.U32
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.R.W.U32_R_R_II_R
R_R_II_R
INT_ARITH
4 ★
SHF.R.W.U32_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
SHF.R.W.U32_R_R_R_R_R
R_R_R_R_R
INT_ARITH
4 ★
SHF.R.W.U32_R_R_UR_UR
R_R_UR_UR
INT_ARITH
4 ★
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
SHF.R.W.U32_R_R_II_R_II_?
R_R_II_R_II_?
INT_ARITH
4 ★
SHF.R.W.U32_R_R_II_R_II_? — 3 fields · 20 samples
and_base: 0x0000000000001e000000001e50007819
var_mask: 0x000000000000007e000000000f7f0000
Bits
W
Tok
Extraction
[70:65]
6
t4
reg
[27:24]
4
t2
reg
[22:16]
7
t1
reg
SHF.R.W.U32_R_R_II_R — 3 fields · 32 samples
and_base: 0x0000000000001e000000001e00007819
var_mask: 0x000000000000007f000000007f7f0000
Bits
W
Tok
Extraction
[70:64]
7
t4
reg
[30:24]
7
t2
reg
[22:16]
7
t1
reg
SHF.R.W.U32_R_R_R_R — 3 fields · 32 samples
and_base: 0x0000000000001e000000003200007219
var_mask: 0x00000000000000ff00000000ff7f0000
Bits
W
Tok
Extraction
[71:64]
8
t4
reg
[31:24]
8
t2
imm
[22:16]
7
t1
reg
SHF.R.W.U32_R_R_R_R_R — 3 fields · 2 samples
and_base: 0x0000000000001e090000003000217219
var_mask: 0x000000000000002000000000ff1e0000
Bits
W
Tok
Extraction
[69]
1
t4
reg
[31:24]
8
t2
imm
[20:17]
4
t1
reg
SHF.R.W.U32_R_R_UR_UR — 3 fields · 32 samples
and_base: 0x0000000008001eff0000000400007c19
var_mask: 0x0000000000000000000000017f7f0000
Bits
W
Tok
Extraction
[32]
1
t3
ureg
[30:24]
7
t2
reg
[22:16]
7
t1
reg
SHF.R.W.U32.HI
Funnel shift. Concatenates Ra:Rb as a 64-bit value and extracts a 32-bit window. .L = shift left (extract from high end), .R = shift right (extract from low end). .HI = use upper 32 bits of the 64-bit source. .CLAMP = clamp shift amount to [0,31].
InsKey
Operands
Pipeline
Latency
SHF.R.W.U32.HI_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
SHF.R.W.U32.HI_R_R_R_R — 3 fields · 8 samples
and_base: 0x0000000000011e0100000000ff017219
var_mask: 0x000000000000000e0000000e001e0000
Bits
W
Tok
Extraction
[67:65]
3
t4
reg
[35:33]
3
t3
reg
[20:17]
4
t1
reg
SHFL
Warp shuffle. Exchanges register values between lanes within a warp. Modes: .IDX (arbitrary lane), .UP (lane+delta), .DOWN (lane-delta), .BFLY (XOR). Used for warp-level reductions and scans without shared memory.
InsKey
Operands
Modifiers
Pipeline
Latency
SHFL_P_R_R_II_II
P_R_R_II_II
IDX, UP, BFLY
WARP_SYNC
5 ~
SHFL_P_R_R_II_R
P_R_R_II_R
UP, IDX, BFLY
WARP_SYNC
5 ~
SHFL_P_R_R_R_II
P_R_R_R_II
IDX, UP, BFLY
WARP_SYNC
5 ~
SHFL_P_R_R_R_R
P_R_R_R_R
BFLY, IDX, UP
WARP_SYNC
5 ~
SHFL_P_R_R_II_II.IDX — 3 fields · 14 samples
and_base: 0x00000000000e000003e01f0000007f89
var_mask: 0x1c0000000000000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[31:24]
8
t3
reg
[23:16]
8
t2
reg
SHFL_P_R_R_II_II.UP — 4 fields · 63 samples
and_base: 0x00000000000000ff0400000000007989
var_mask: 0x1c0000000000000003e00000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[57:53]
5
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t2
reg
SHFL_P_R_R_II_II.BFLY — 9 fields · 150 samples
and_base: 0x400000c00000000007389
var_mask: 0x1c0000000002001f0000001f1f1d0000
Bits
W
Tok
Extraction
[124]
1
t5
reuse
[123]
1
t4
reuse
[122]
1
t3
reuse
[81]
1
t1
pred
[68:64]
5
t5
reg
[36:32]
5
t4
reg
[28:24]
5
t3
reg
[20:18]
3
t0
[16]
1
t1
pred
SHFL_P_R_R_II_R.UP — 4 fields · 63 samples
and_base: 0x00000000000000ff0400000000007989
var_mask: 0x1c0000000000000003e00000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[57:53]
5
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t2
reg
SHFL_P_R_R_II_R.IDX — 3 fields · 14 samples
and_base: 0x00000000000e000003e01f0000007f89
var_mask: 0x1c0000000000000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[31:24]
8
t3
reg
[23:16]
8
t2
reg
SHFL_P_R_R_II_R.BFLY — 9 fields · 150 samples
and_base: 0x400000c00000000007389
var_mask: 0x1c0000000002001f0000001f1f1d0000
Bits
W
Tok
Extraction
[124]
1
t5
reuse
[123]
1
t4
reuse
[122]
1
t3
reuse
[81]
1
t1
pred
[68:64]
5
t5
reg
[36:32]
5
t4
reg
[28:24]
5
t3
reg
[20:18]
3
t0
[16]
1
t1
pred
SHFL_P_R_R_R_II.IDX — 5 fields · 139 samples
and_base: 0x00000000000e000000001f0000007589
var_mask: 0x1c00000000000000000000ffffff0000
Bits
W
Tok
Extraction
[123]
1
t4
reuse
[122]
1
t3
reuse
[39:32]
8
t4
reg
[31:24]
8
t3
reg
[23:16]
8
t2
reg
SHFL_P_R_R_R_II.UP — 4 fields · 63 samples
and_base: 0x00000000000000ff0400000000007989
var_mask: 0x1c0000000000000003e00000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[57:53]
5
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t2
reg
SHFL_P_R_R_R_II.BFLY — 9 fields · 150 samples
and_base: 0x400000c00000000007389
var_mask: 0x1c0000000002001f0000001f1f1d0000
Bits
W
Tok
Extraction
[124]
1
t5
reuse
[123]
1
t4
reuse
[122]
1
t3
reuse
[81]
1
t1
pred
[68:64]
5
t5
reg
[36:32]
5
t4
reg
[28:24]
5
t3
reg
[20:18]
3
t0
[16]
1
t1
pred
SHFL_P_R_R_R_R.BFLY — 9 fields · 150 samples
and_base: 0x400000c00000000007389
var_mask: 0x1c0000000002001f0000001f1f1d0000
Bits
W
Tok
Extraction
[124]
1
t5
reuse
[123]
1
t4
reuse
[122]
1
t3
reuse
[81]
1
t1
pred
[68:64]
5
t5
reg
[36:32]
5
t4
reg
[28:24]
5
t3
reg
[20:18]
3
t0
[16]
1
t1
pred
SHFL_P_R_R_R_R.IDX — 3 fields · 14 samples
and_base: 0x00000000000e000003e01f0000007f89
var_mask: 0x1c0000000000000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[31:24]
8
t3
reg
[23:16]
8
t2
reg
SHFL_P_R_R_R_R.UP — 4 fields · 63 samples
and_base: 0x00000000000000ff0400000000007989
var_mask: 0x1c0000000000000003e00000ffff0000
Bits
W
Tok
Extraction
[122]
1
t3
reuse
[57:53]
5
t4
imm
[31:24]
8
t3
reg
[23:16]
8
t2
reg
SHFL.BFLY
Warp shuffle. Exchanges register values between lanes within a warp. Modes: .IDX (arbitrary lane), .UP (lane+delta), .DOWN (lane-delta), .BFLY (XOR). Used for warp-level reductions and scans without shared memory.
InsKey
Operands
Pipeline
Latency
SHFL.BFLY_P_R_R_II_II
P_R_R_II_II
WARP_SYNC
5 ~
SHFL.BFLY_P_R_R_R_R
P_R_R_R_R
WARP_SYNC
5 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
SHFL.BFLY_P_R_R_II_II_?
P_R_R_II_II_?
WARP_SYNC
5 ~
SHFL.BFLY_P_R_R_II_II_? — 3 fields · 15 samples
and_base: 0x00000000000e00000c001f0000007f89
var_mask: 0x000000000000000000e000001f1e0000
Bits
W
Tok
Extraction
[55:53]
3
t4
imm
[28:24]
5
t3
reg
[20:17]
4
t2
reg
SHFL.BFLY_P_R_R_II_II — 3 fields · 32 samples
and_base: 0x00000000000e00000c001f0000007f89
var_mask: 0x000000000000000000e000001f1f0000
Bits
W
Tok
Extraction
[55:53]
3
t4
imm
[28:24]
5
t3
reg
[20:16]
5
t2
reg
SHFL.BFLY_P_R_R_R_R — 5 fields · 32 samples
and_base: 0x00000000000000140c00001010107389
var_mask: 0x00000000000600010000000703020000
Bits
W
Tok
Extraction
[82:81]
2
t1
pred
[64]
1
t5
reg
[34:32]
3
t4
reg
[25:24]
2
t3
reg
[17]
1
t2
reg
SHFL.IDX
Warp shuffle. Exchanges register values between lanes within a warp. Modes: .IDX (arbitrary lane), .UP (lane+delta), .DOWN (lane-delta), .BFLY (XOR). Used for warp-level reductions and scans without shared memory.
InsKey
Operands
Pipeline
Latency
SHFL.IDX_P_R_R_II_II
P_R_R_II_II
WARP_SYNC
5 ~
SHFL.IDX_P_R_R_R_II
P_R_R_R_II
WARP_SYNC
5 ~
2 partial encodings — operand types not fully identified
InsKey
Operands
Pipeline
Latency
SHFL.IDX_P_R_R_II_II_?
P_R_R_II_II_?
WARP_SYNC
5 ~
SHFL.IDX_P_R_R_R_II_?
P_R_R_R_II_?
WARP_SYNC
5 ~
SHFL.IDX_P_R_R_II_II_? — 2 fields · 7 samples
and_base: 0x00000000000e000003e01f0010187f89
var_mask: 0x0000000000000000000000000e030000
Bits
W
Tok
Extraction
[27:25]
3
t3
reg
[17:16]
2
t2
reg
SHFL.IDX_P_R_R_II_II — 2 fields · 18 samples
and_base: 0x00000000000e000003e01f0000007f89
var_mask: 0x0000000000000000000000001e1f0000
Bits
W
Tok
Extraction
[28:25]
4
t3
reg
[20:16]
5
t2
reg
SHFL.IDX_P_R_R_R_II — 3 fields · 32 samples
and_base: 0x00000000000e000000001f0000007589
var_mask: 0x0000000000000000000000ff7f7f0000
Bits
W
Tok
Extraction
[39:32]
8
t4
imm
[30:24]
7
t3
reg
[22:16]
7
t2
reg
SHFL.UP
Warp shuffle. Exchanges register values between lanes within a warp. Modes: .IDX (arbitrary lane), .UP (lane+delta), .DOWN (lane-delta), .BFLY (XOR). Used for warp-level reductions and scans without shared memory.
InsKey
Operands
Pipeline
Latency
SHFL.UP_P_R_R_II_II
P_R_R_II_II
WARP_SYNC
5 ~
SHFL.UP_P_R_R_II_II — 3 fields · 32 samples
and_base: 0x00000000000000ff0400000001007989
var_mask: 0x000000000000000003e000001e1f0000
Bits
W
Tok
Extraction
[57:53]
5
t4
imm
[28:25]
4
t3
reg
[20:16]
5
t2
reg
ST
Generic store.
InsKey
Operands
Modifiers
Pipeline
Latency
ST_ARI_R
ARI_R
64,E, E, E,U8
MEMORY
0 ~
ST_dARI_R
dARI_R
64,E, E, E,U8
MEMORY
0 ~
ST_ARI_R.64,E — 5 fields · 150 samples
and_base: 0x100b000000000000000385
var_mask: 0x1c0000000000005e00000100fe00f000
Bits
W
Tok
Extraction
[70]
1
t1
reg
[68:65]
4
t0
[40]
1
t0
[31:25]
7
t0
[15:12]
4
t0
guard
ST_ARI_R.E — 6 fields · 175 samples
and_base: 0x000000000c1019000000000004007985
var_mask: 0x1c000000000000ffffffffffff000000
Bits
W
Tok
Extraction
[124]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t2
reg
[63:40]
24
t1
sub_imm2
[39:32]
8
t1
imm
[31:24]
8
t1
reg
ST_ARI_R.E,U8 — 6 fields · 29 samples
and_base: 0x000000000c1011000000400100001985
var_mask: 0x1c000000000000ff000000feff00f000
Bits
W
Tok
Extraction
[124]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t2
reg
[39:32]
8
t1
imm
[31:24]
8
t1
reg
[15:12]
4
t0
guard
ST_dARI_R.64,E — 7 fields · 44 samples
and_base: 0x000000000c101b000000000000007985
var_mask: 0x1c000000000000ffffffffffff000000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t1
sub_ur0
[63:40]
24
t1
sub_imm2
[39:32]
8
t2
reg
[31:24]
8
t1
sub_r1
ST_dARI_R.E — 7 fields · 175 samples
and_base: 0x000000000c1019000000000004007985
var_mask: 0x1c000000000000ffffffffffff000000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t1
sub_ur0
[63:40]
24
t1
sub_imm2
[39:32]
8
t2
reg
[31:24]
8
t1
sub_r1
ST_dARI_R.E,U8 — 7 fields · 29 samples
and_base: 0x000000000c1011000000400100001985
var_mask: 0x1c000000000000ff000000ffff00f000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t1
sub_ur0
[39:32]
8
t2
reg
[31:24]
8
t1
sub_r1
[15:12]
4
t0
guard
ST.E
Generic store.
InsKey
Operands
Pipeline
Latency
ST.E_dARI_R
dARI_R
MEMORY
0 ~
ST.E_dARI_R — 3 fields · 32 samples
and_base: 0x000000000c1019000000000100007985
var_mask: 0x000000000000000e0000000e7e000000
Bits
W
Tok
Extraction
[67:65]
3
t1
ureg
[35:33]
3
t2
reg
[30:25]
6
t1
reg
ST.E.128
Generic store.
InsKey
Operands
Pipeline
Latency
ST.E.128_dARI_R
dARI_R
MEMORY
0 ~
ST.E.128_dARI_R — 4 fields · 32 samples
and_base: 0x000000000c101d000000000000000985
var_mask: 0x000000000000001e0000001c7e007000
Bits
W
Tok
Extraction
[68:65]
4
t1
ureg
[36:34]
3
t2
reg
[30:25]
6
t1
reg
[14:12]
3
t0
guard
ST.E.64
Generic store.
InsKey
Operands
Pipeline
Latency
ST.E.64_dARI_R
dARI_R
MEMORY
0 ~
ST.E.64_dARI_R — 4 fields · 32 samples
and_base: 0x000000000c101b000000000000007985
var_mask: 0x000000000000001e0000787e3e000000
Bits
W
Tok
Extraction
[68:65]
4
t1
ureg
[46:43]
4
t1
imm
[38:33]
6
t2
reg
[29:25]
5
t1
reg
ST.E.U16
Generic store.
InsKey
Operands
Pipeline
Latency
ST.E.U16_dARI_R
dARI_R
MEMORY
0 ~
ST.E.U16_dARI_R — 4 fields · 32 samples
and_base: 0x000000000c10151c0000000010000985
var_mask: 0x000000000000000000007e3f0e00f000
Bits
W
Tok
Extraction
[46:41]
6
t1
imm
[37:32]
6
t2
reg
[27:25]
3
t1
reg
[15:12]
4
t0
guard
ST.E.U8
Generic store.
InsKey
Operands
Pipeline
Latency
ST.E.U8_dARI_R
dARI_R
MEMORY
0 ~
ST.E.U8_dARI_R — 5 fields · 32 samples
and_base: 0x000000000c1011080000000000000985
var_mask: 0x00000000000000060000017f7e00f000
Bits
W
Tok
Extraction
[66:65]
2
t1
ureg
[40]
1
t1
imm
[38:32]
7
t2
reg
[30:25]
6
t1
reg
[15:12]
4
t0
guard
STG
Store to global memory via descriptor.
InsKey
Operands
Modifiers
Pipeline
Latency
STG_ARI_R
ARI_R
128,E, E,GPU,STRONG, 128,E,EF, 64,E, E
MEMORY
0 ~
STG_dARI_R
dARI_R
128,E, 128,E,EF, 64,E, E, E,GPU,STRONG
MEMORY
0 ~
STG_ARI_R.128,E — 9 fields · 143 samples
and_base: 0x100d000000000000000186
var_mask: 0x1c0000000c00001c0000005c9e005a00
Bits
W
Tok
Extraction
[91:90]
2
t0
[68:66]
3
t0
[38]
1
t1
reg
[36:34]
3
t0
[31]
1
t1
reg
[28:25]
4
t0
[14]
1
t1
reg
[12:11]
2
t0
[9]
1
t0
STG_ARI_R.E,GPU,STRONG — 20 fields · 7 samples
and_base: 0x10e900000000035c008386
var_mask: 0x1c0000000071eb00000000ffff00f011
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t1
reuse
[86]
1
t1
reg
[85]
1
t1
reg
[84]
1
t2
reg
[80]
1
t1
reg
[79]
1
t1
reg
[78]
1
t1
reg
[77]
1
t1
reg
[75]
1
t2
reg
[74]
1
t0
neg
[73]
1
t1
reg
[72]
1
t2
reg
[63:40]
24
t1
imm
[39:32]
8
t2
reg
[31:24]
8
t1
reg
[15:12]
4
t0
guard
[7:6]
2
t0
[4]
1
t1
reg
[0]
1
t1
reg
STG_ARI_R.128,E,EF — 9 fields
and_base: 0x0000000000001d020000002000008986
var_mask: 0x1ffffe000c00001c0000005c9e005000
Bits
W
Tok
Extraction
[91:90]
2
t0
[68:66]
3
t0
[38]
1
t1
reg
[36:34]
3
t0
[31]
1
t1
reg
[28:25]
4
t0
[14]
1
t1
reg
[12:11]
2
t0
[9]
1
t0
STG_ARI_R.64,E — 11 fields
and_base: 0x0000000000101b020010000000002986
var_mask: 0x1ffffe000c00001c0000087ebe005000
Bits
W
Tok
Extraction
[91:90]
2
t0
[68:66]
3
t0
[43]
1
t1
imm
[38]
1
t1
reg
[36:34]
3
t0
[33]
1
t1
imm
[31]
1
t1
reg
[28:25]
4
t0
[14]
1
t1
reg
[12:11]
2
t0
[9]
1
t0
STG_ARI_R.E — 7 fields · 536 samples
and_base: 0x000000000c1019000000000000007986
var_mask: 0x1c000000000000ff0001fcffff000000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t1
sub_ur0
[63:40]
24
t1
imm
[39:32]
8
t2
reg
[31:24]
8
t1
reg
STG_dARI_R.128,E — 6 fields
and_base: 0x000000000c101d000000000000000986
var_mask: 0x1ffffe000000003e000000fffe00f000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[69:65]
5
t1
sub_ur0_shr1
[39:32]
8
t2
reg
[31:25]
7
t1
sub_r1_shr1
[15:12]
4
t0
guard
[9]
1
t0
STG_dARI_R.128,E,EF — 5 fields · 1 samples
and_base: 0x000000000c001d000000000000000986
var_mask: 0x1c0000000000003e000000fffe00f000
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[69:65]
5
t1
sub_ur0_shr1
[39:32]
8
t2
reg
[31:25]
7
t1
sub_r1_shr1
[15:12]
4
t0
guard
STG_dARI_R.64,E — 10 fields · 454 samples
and_base: 0x000000000c101b000000000000000986
var_mask: 0x1c000000000000ffffffffffff00f000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[69:65]
5
t1
sub_ur0_shr1
[71:64]
8
t1
sub_ur0
[63:40]
24
t1
sub_imm2
[39:32]
8
t2
reg
[31:25]
7
t1
sub_r1_shr1
[31:24]
8
t1
sub_r1
[15:12]
4
t0
guard
STG_dARI_R.E — 10 fields · 536 samples
and_base: 0x000000000c1019000000000000000986
var_mask: 0x1c000000000000ffffffffffff00f000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[69:65]
5
t1
sub_ur0_shr1
[71:64]
8
t1
sub_ur0
[63:40]
24
t1
sub_imm2
[39:32]
8
t2
reg
[31:25]
7
t1
sub_r1_shr1
[31:24]
8
t1
sub_r1
[15:12]
4
t0
guard
STG_dARI_R.E,GPU,STRONG — 20 fields · 7 samples
and_base: 0x000000000010e900000000035c000386
var_mask: 0x1c0000000071eb00000000ffff00f011
Bits
W
Tok
Extraction
[123]
1
t2
reuse
[122]
1
t1
reuse
[86]
1
t2
reg
[85]
1
t2
reg
[84]
1
t2
reg
[80]
1
t2
reg
[79]
1
t2
reg
[78]
1
t2
reg
[77]
1
t2
reg
[75]
1
t2
reg
[74]
1
t0
neg
[73]
1
t2
reg
[72]
1
t2
reg
[63:40]
24
t1
imm
[39:32]
8
t2
reg
[31:24]
8
t1
reg
[15:12]
4
t0
guard
[7:6]
2
t0
[4]
1
t2
reg
[0]
1
t2
reg
STG.E
Store to global memory via descriptor.
InsKey
Operands
Pipeline
Latency
STG.E_II_R
II_R
MEMORY
0 ~
STG.E_P_dARI_R
P_dARI_R
MEMORY
0 ~
STG.E_dARI_R
dARI_R
MEMORY
0 ~
STG.E_dARI_R_R
dARI_R_R
MEMORY
0 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
STG.E_dARI_R_II_?
dARI_R_II_?
MEMORY
0 ~
STG.E_dARI_R_II_? — 8 fields · 1 samples
and_base: 0x000000000c1019000000000000000986
var_mask: 0x1c000000000000ffffffffffff00f000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t1
ureg
[63:40]
24
t1
imm
[39:32]
8
t2
reg
[31:24]
8
t1
reg
[15:12]
4
t0
guard
STG.E_II_R — 8 fields
and_base: 0xc0010000000000000000986
var_mask: 0x1c000000000000ffffffffffff00f000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t1
ureg
[63:40]
24
t1
imm
[39:32]
8
t2
reg
[31:24]
8
t1
reg
[15:12]
4
t0
guard
STG.E_P_dARI_R — 5 fields
and_base: 0xc0010000000000000000986
var_mask: 0x1c000000000000ffffffffffff00f000
Bits
W
Tok
Extraction
[71:64]
8
t1
ureg
[63:40]
24
t1
imm
[39:32]
8
t2
reg
[31:24]
8
t1
reg
[15:12]
4
t0
guard
STG.E_dARI_R — 8 fields
and_base: 0xc0010000000000000000986
var_mask: 0x1c000000000000ffffffffffff00f000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[123]
1
t2
reuse
[122]
1
t1
reuse
[71:64]
8
t1
ureg
[63:40]
24
t1
imm
[39:32]
8
t2
reg
[31:24]
8
t1
reg
[15:12]
4
t0
guard
STG.E_dARI_R_R — 3 fields · 12 samples
and_base: 0x000000000c1019000000000100007986
var_mask: 0x000000000000000e000000fe1e000000
Bits
W
Tok
Extraction
[67:65]
3
t1
ureg
[39:33]
7
t2
reg
[28:25]
4
t1
reg
STG.E.128
Store to global memory via descriptor.
InsKey
Operands
Pipeline
Latency
STG.E.128_dARI_R
dARI_R
MEMORY
4 ~
STG.E.128_dARI_R_R
dARI_R_R
MEMORY
4 ~
STG.E.128_dARI_R — 6 fields
and_base: 0xc001000000000ff00000986
var_mask: 0x1c000000000000ffffffff00ff00f000
Bits
W
Tok
Extraction
[124]
1
t1
reuse
[122]
1
t1
reuse
[71:64]
8
t1
ureg
[63:40]
24
t1
imm
[31:24]
8
t1
reg
[15:12]
4
t0
guard
STG.E.128_dARI_R_R — 3 fields · 11 samples
and_base: 0x000000000c101d000000000000007986
var_mask: 0x000000000000003e0000003c3e000000
Bits
W
Tok
Extraction
[69:65]
5
t1
ureg
[37:34]
4
t2
reg
[29:25]
5
t1
reg
STG.E.64
Store to global memory via descriptor.
InsKey
Operands
Pipeline
Latency
STG.E.64_dARI_R
dARI_R
MEMORY
0 ~
STG.E.64_dARI_R_R
dARI_R_R
MEMORY
0 ~
1 partial encoding — operand types not fully identified
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
USEL_UR_UR_II_?
UR_UR_II_?
INT_ARITH
4 ★
USEL_UR_UR_II_? — 1 fields · 32 samples
and_base: 0x000000000c00000000000001ff017887
var_mask: 0x000000000000000000000000000e0000
Bits
W
Tok
Extraction
[19:17]
3
t1
ureg
USEL_UR_UR_II_II — 3 fields · 32 samples
and_base: 0x000000000c0000000000000000007887
var_mask: 0x0000000000000000ffffffff1f1f0000
Bits
W
Tok
Extraction
[63:32]
32
t3
imm
[28:24]
5
t2
ureg
[20:16]
5
t1
ureg
USEL_UR_UR_II_UP — 5 fields · 17 samples
and_base: 0x00000000080000000000000004007887
var_mask: 0x1c0000000380000080808082ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[89:87]
3
t4
pred
[63:32]
32
t3
imm
[31:24]
8
t2
ureg_ff
[23:16]
8
t1
ureg
USEL_UR_UR_UR_UP — 4 fields · 11 samples
and_base: 0x000000000c000000000000ff04087287
var_mask: 0x1c0000000380000000000000ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[89:87]
3
t4
pred
[31:24]
8
t2
ureg
[23:16]
8
t1
ureg
USEL.64
Uniform select.
InsKey
Operands
Pipeline
Latency
USEL.64_UR_UR_II_UP
UR_UR_II_UP
INT_ARITH
4 ★
USEL.64_UR_UR_UR_UP
UR_UR_UR_UP
INT_ARITH
4 ★
USEL.64_UR_UR_UR_UR
UR_UR_UR_UR
INT_ARITH
4 ★
USEL.64_UR_UR_II_UP — 3 fields · 29 samples
and_base: 0x000000000c0000000000000100007487
var_mask: 0x0000000000800000000000003e3e0000
Bits
W
Tok
Extraction
[87]
1
t4
upred
[29:25]
5
t2
ureg
[21:17]
5
t1
ureg
USEL.64_UR_UR_UR_UR — 3 fields · 32 samples
and_base: 0x000000000c0000000000000000007c87
var_mask: 0x00000000000000000000003e1e3e0000
Bits
W
Tok
Extraction
[37:33]
5
t3
ureg
[28:25]
4
t2
ureg
[21:17]
5
t1
ureg
USETMAXREG.DEALLOC.CTAPOOL
Warpgroup maximum register control. SM120 implementation of setmaxnreg.inc/dec.sync. .TRY_ALLOC requests additional registers for the warp group; .DEALLOC returns them. Used to manage register file partitioning between producer and consumer warp groups in warpgroup MMA pipelines.
InsKey
Operands
Pipeline
Latency
USETMAXREG.DEALLOC.CTAPOOL_II
II
BARRIER
2 ~
USETMAXREG.DEALLOC.CTAPOOL_II — 2 fields
and_base: 0x80e010000000000000009c8
var_mask: 0x1c00000000000000000003ff0000f000
Bits
W
Tok
Extraction
[41:32]
10
t1
imm
[15:12]
4
t0
guard
USETMAXREG.TRY
Warpgroup maximum register control. SM120 implementation of setmaxnreg.inc/dec.sync. .TRY_ALLOC requests additional registers for the warp group; .DEALLOC returns them. Used to manage register file partitioning between producer and consumer warp groups in warpgroup MMA pipelines.
Flush pending TMA commands. Ensures all preceding TMA operations are committed before this point.
InsKey
Operands
Pipeline
Latency
UTMACMDFLUSH
OMMA
2 ~
UTMACMDFLUSH — 1 fields
and_base: 0x9b7
var_mask: 0x1c00000000000000000000000000f000
Bits
W
Tok
Extraction
[15:12]
4
t0
guard
UTMALDG.1D
TMA (Tensor Memory Accelerator) load from global memory to shared memory. SM120 implementation of cp.async.bulk.tensor. .1D/.2D specifies tensor dimensionality. Asynchronous: result available after mbarrier completion.
InsKey
Operands
Pipeline
Latency
UTMALDG.1D_AUR_AUR
AUR_AUR
OMMA
5 ~
UTMALDG.1D_AUR_AUR — 3 fields
and_base: 0x800000000000000000005b4
var_mask: 0x1c00000000000000000000ffff00f000
Bits
W
Tok
Extraction
[39:32]
8
t1
ureg
[31:24]
8
t2
ureg
[15:12]
4
t0
guard
UTMALDG.2D
TMA (Tensor Memory Accelerator) load from global memory to shared memory. SM120 implementation of cp.async.bulk.tensor. .1D/.2D specifies tensor dimensionality. Asynchronous: result available after mbarrier completion.
InsKey
Operands
Pipeline
Latency
UTMALDG.2D_AUR_AUR
AUR_AUR
OMMA
5 ~
UTMALDG.2D_AUR_AUR — 3 fields
and_base: 0x800000000000000000005b4
var_mask: 0x1c00000000000000000000ffff00f000
Bits
W
Tok
Extraction
[39:32]
8
t1
ureg
[31:24]
8
t2
ureg
[15:12]
4
t0
guard
UVIMNMX
Uniform SIMD integer min/max.
InsKey
Operands
Modifiers
Pipeline
Latency
UVIMNMX_UR_UR_II_P
UR_UR_II_P
S32
INT_ARITH
4 ~
UVIMNMX_UR_UR_II_UP
UR_UR_II_UP
U32, S32
INT_ARITH
4 ~
UVIMNMX_UR_UR_UR_P
UR_UR_UR_P
S32
INT_ARITH
4 ~
UVIMNMX_UR_UR_UR_UP
UR_UR_UR_UP
S32, U32
INT_ARITH
4 ~
UVIMNMX_UR_UR_II_P.S32 — 7 fields
and_base: 0x87e0000000000000000084a
var_mask: 0x1c00000007800000fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[90]
1
t4
neg
[89:87]
3
t4
upred
[63:32]
32
t3
imm
[31:24]
8
t2
ureg
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
UVIMNMX_UR_UR_II_UP.U32 — 5 fields · 13 samples
and_base: 0x000000000bfe0000000000000000784a
var_mask: 0x1c0000000400000000000003ffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[90]
1
t3
imm
[63:32]
32
t3
imm
[31:24]
8
t2
ureg
[23:16]
8
t1
ureg
UVIMNMX_UR_UR_II_UP.S32 — 3 fields · 136 samples
and_base: 0xbfe0100000000000000724a
var_mask: 0x1c000000040000000000001fff1f0000
Bits
W
Tok
Extraction
[90]
1
t1
ureg
[36:24]
13
t0
[20:16]
5
t1
ureg
UVIMNMX_UR_UR_UR_P.S32 — 8 fields
and_base: 0x87e0000000000000000024a
var_mask: 0x1c00000007800000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[90]
1
t4
neg
[89:87]
3
t4
upred
[39:32]
8
t3
ureg
[31:24]
8
t2
ureg
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
UVIMNMX_UR_UR_UR_UP.S32 — 3 fields · 136 samples
and_base: 0xbfe0100000000000000724a
var_mask: 0x1c000000040000000000001fff1f0000
Bits
W
Tok
Extraction
[90]
1
t1
ureg
[36:24]
13
t0
[20:16]
5
t1
ureg
UVIMNMX_UR_UR_UR_UP.U32 — 13 fields · 14 samples
and_base: 0x87e000000000000ff00024a
var_mask: 0x1c0000000780170000000001fffff004
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t1
reuse
[90]
1
t1
ureg
[89:87]
3
t4
pred
[76]
1
t1
ureg
[74]
1
t1
ureg
[73]
1
t1
ureg
[72]
1
t3
ureg
[32]
1
t3
ureg
[31:24]
8
t1
ureg
[23:16]
8
t1
ureg
[15:12]
4
t4
pred
[2]
1
t1
ureg
UVIMNMX.S32
Uniform SIMD integer min/max.
InsKey
Operands
Pipeline
Latency
UVIMNMX.S32_UR_UR_II_UP
UR_UR_II_UP
INT_ARITH
4 ~
UVIMNMX.S32_UR_UR_UR_UP
UR_UR_UR_UP
INT_ARITH
4 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
UVIMNMX.S32_UR_UR_II_?
UR_UR_II_?
INT_ARITH
4 ~
UVIMNMX.S32_UR_UR_II_? — 2 fields · 32 samples
and_base: 0x000000000ffe0100000000010000784a
var_mask: 0x0000000000000000000000001f1f0000
Bits
W
Tok
Extraction
[28:24]
5
t2
ureg
[20:16]
5
t1
ureg
UVIMNMX.S32_UR_UR_II_UP — 3 fields · 32 samples
and_base: 0x000000000bfe0100000000010000784a
var_mask: 0x0000000000000000000000061f1f0000
Bits
W
Tok
Extraction
[34:33]
2
t3
imm
[28:24]
5
t2
ureg
[20:16]
5
t1
ureg
UVIMNMX.S32_UR_UR_UR_UP — 3 fields · 32 samples
and_base: 0x000000000bfe0100000000000000724a
var_mask: 0x00000000000000000000001f0f1f0000
Bits
W
Tok
Extraction
[36:32]
5
t3
ureg
[27:24]
4
t2
ureg
[20:16]
5
t1
ureg
UVIMNMX.U32
Uniform SIMD integer min/max.
InsKey
Operands
Pipeline
Latency
UVIMNMX.U32_UR_UR_II_UP
UR_UR_II_UP
INT_ARITH
4 ~
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
UVIMNMX.U32_UR_UR_II_?
UR_UR_II_?
INT_ARITH
4 ~
UVIMNMX.U32_UR_UR_II_? — 2 fields · 3 samples
and_base: 0x000000000ffe0000000000013d04784a
var_mask: 0x00000000000000000000000002010000
Bits
W
Tok
Extraction
[25]
1
t2
ureg
[16]
1
t1
ureg
UVIMNMX.U32_UR_UR_II_UP — 2 fields · 2 samples
and_base: 0x000000000bfe0000000000020200784a
var_mask: 0x0000000000000000000000001c0f0000
Bits
W
Tok
Extraction
[28:26]
3
t2
ureg
[19:16]
4
t1
ureg
VIADD.U8x4
InsKey
Operands
Pipeline
Latency
VIADD.U8x4_R_R_R
R_R_R
INT_ARITH
4 ~
VIADD.U8x4_R_R_R — 10 fields
and_base: 0x236
var_mask: 0x1c00000000000100800000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[72]
1
t2
neg
[63]
1
t3
neg
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
VIMNMX
Vector integer min/max. Operates on packed sub-word integers. .S32: two packed 16-bit signed comparisons, or one 32-bit. Used for packed integer processing without unpacking.
InsKey
Operands
Modifiers
Pipeline
Latency
VIMNMX_R_R_II_P
R_R_II_P
U32, S32
INT_ARITH
4 ★
VIMNMX_R_R_R_P
R_R_R_P
S32, U32
INT_ARITH
4 ★
VIMNMX_R_R_UR_P
R_R_UR_P
S32, U32
INT_ARITH
4 ★
VIMNMX_R_R_II_P.U32 — 5 fields · 29 samples
and_base: 0x0000000003fe00000000000000007848
var_mask: 0x1c000000040000000003ffffffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[90]
1
t4
inv
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
VIMNMX_R_R_II_P.S32 — 5 fields · 5 samples
and_base: 0x0000000003fe01000000000302007248
var_mask: 0x1c00000004000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[90]
1
t4
inv
[39:32]
8
t3
reg
[23:16]
8
t1
reg
VIMNMX_R_R_R_P.S32 — 5 fields · 5 samples
and_base: 0x0000000003fe01000000000302007248
var_mask: 0x1c00000004000000000000ff00ff0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[90]
1
t4
inv
[39:32]
8
t3
reg
[23:16]
8
t1
reg
VIMNMX_R_R_R_P.U32 — 5 fields · 29 samples
and_base: 0x0000000003fe00000000000000007848
var_mask: 0x1c000000040000000003ffffffff0000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[90]
1
t4
inv
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
VIMNMX_R_R_UR_P.S32 — 5 fields · 148 samples
and_base: 0xbfe01000000000000007c48
var_mask: 0x1c000000000000000000000f3f3f0000
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[35:32]
4
t3
ureg
[29:24]
6
t2
reg
[21:16]
6
t1
reg
VIMNMX_R_R_UR_P.U32 — 16 fields · 2 samples
and_base: 0x87e00000000000000000c48
var_mask: 0x1c000000078017000000000b0901f048
Bits
W
Tok
Extraction
[123]
1
t3
reuse
[122]
1
t2
reuse
[90]
1
t2
neg
[89:87]
3
t4
pred
[76]
1
t2
neg
[74]
1
t2
neg
[73]
1
t2
neg
[72]
1
t4
neg
[35]
1
t3
ureg
[33:32]
2
t3
ureg
[27]
1
t2
reg
[24]
1
t1
reg
[16]
1
t1
reg
[15:12]
4
t4
pred
[6]
1
t4
pred
[3]
1
t4
pred
VIMNMX.S32
Vector integer min/max. Operates on packed sub-word integers. .S32: two packed 16-bit signed comparisons, or one 32-bit. Used for packed integer processing without unpacking.
InsKey
Operands
Pipeline
Latency
VIMNMX.S32_R_R_II_II
R_R_II_II
INT_ARITH
4 ★
VIMNMX.S32_R_R_R_P
R_R_R_P
INT_ARITH
4 ★
VIMNMX.S32_R_R_R_R
R_R_R_R
INT_ARITH
4 ★
VIMNMX.S32_R_R_UR_P
R_R_UR_P
INT_ARITH
4 ★
VIMNMX.S32_R_R_UR_UR
R_R_UR_UR
INT_ARITH
4 ★
10 partial encodings — operand types not fully identified
Vector integer min/max. Operates on packed sub-word integers. .S32: two packed 16-bit signed comparisons, or one 32-bit. Used for packed integer processing without unpacking.
InsKey
Operands
Pipeline
Latency
VIMNMX.U32_R_R_II_II
R_R_II_II
INT_ARITH
4 ~
VIMNMX.U32_R_R_II_P
R_R_II_P
INT_ARITH
4 ~
VIMNMX.U32_R_R_II_P_P
R_R_II_P_P
INT_ARITH
4 ~
VIMNMX.U32_R_R_II_II — 3 fields · 32 samples
and_base: 0x0000000003fe00000000000f00007848
var_mask: 0x00000000000000000003fff07f7f0000
Bits
W
Tok
Extraction
[49:36]
14
t3
imm
[30:24]
7
t2
reg
[22:16]
7
t1
reg
VIMNMX.U32_R_R_II_P — 7 fields
and_base: 0x7e00000000000000000848
var_mask: 0x1c00000007800000fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[90]
1
t4
neg
[89:87]
3
t4
pred
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
VIMNMX.U32_R_R_II_P_P — 7 fields · 1 samples
and_base: 0x00000000007e00000000000000000848
var_mask: 0x1c00000007800000fffffffffffff000
Bits
W
Tok
Extraction
[122]
1
t2
reuse
[90]
1
t4
neg
[89:87]
3
t4
pred
[63:32]
32
t3
imm
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
VIMNMX.U8x4
Vector integer min/max. Operates on packed sub-word integers. .S32: two packed 16-bit signed comparisons, or one 32-bit. Used for packed integer processing without unpacking.
InsKey
Operands
Pipeline
Latency
VIMNMX.U8x4_R_R_R_P
R_R_R_P
INT_ARITH
4 ~
VIMNMX.U8x4_R_R_R_P — 11 fields
and_base: 0x7e00000000000000000248
var_mask: 0x1c00200007800000000000fffffff000
Bits
W
Tok
Extraction
[123]
1
t3
neg
[123]
1
t3
reuse
[122]
1
t2
neg
[122]
1
t2
reuse
[109]
1
t2
neg
[90]
1
t4
neg
[89:87]
3
t4
pred
[39:32]
8
t3
reg
[31:24]
8
t2
reg
[23:16]
8
t1
reg
[15:12]
4
t0
guard
VOTE
Warp vote. Computes ALL, ANY, or BALLOT across warp threads.
InsKey
Operands
Modifiers
Pipeline
Latency
VOTE_R_P_P
R_P_P
ANY
WARP_SYNC
5 ~
VOTE_R_P_P.ANY — 1 fields · 10 samples
and_base: 0x00000000038e01000000000000007806
var_mask: 0x1c000000000000000000000000ff0000
Bits
W
Tok
Extraction
[23:16]
8
t1
reg
VOTE.ALL
Warp vote. Computes ALL, ANY, or BALLOT across warp threads.
InsKey
Operands
Pipeline
Latency
VOTE.ALL_P_P
P_P
WARP_SYNC
5 ~
VOTE.ALL_P_P — 4 fields
and_base: 0xff0806
var_mask: 0x1c000000078e0000000000000000f000
Bits
W
Tok
Extraction
[90]
1
t2
neg
[89:87]
3
t2
pred
[83:81]
3
t1
pred
[15:12]
4
t0
guard
VOTE.ANY
Warp vote. Computes ALL, ANY, or BALLOT across warp threads.
InsKey
Operands
Pipeline
Latency
VOTE.ANY_P_P
P_P
WARP_SYNC
5 ~
VOTE.ANY_R_P_P
R_P_P
WARP_SYNC
5 ~
VOTE.ANY_P_P — 4 fields
and_base: 0xff0806
var_mask: 0x1c000000078e0000000000000000f000
Bits
W
Tok
Extraction
[90]
1
t2
neg
[89:87]
3
t2
pred
[83:81]
3
t1
pred
[15:12]
4
t0
guard
VOTE.ANY_R_P_P — 5 fields
and_base: 0x806
var_mask: 0x1c000000078e00000000000000fff000
Bits
W
Tok
Extraction
[90]
1
t3
neg
[89:87]
3
t3
pred
[83:81]
3
t2
pred
[23:16]
8
t1
reg
[15:12]
4
t0
guard
VOTEU
Uniform warp vote.
InsKey
Operands
Modifiers
Pipeline
Latency
VOTEU_UP_P
UP_P
ALL, ANY
WARP_SYNC
5 ~
VOTEU_UR_UP_P
UR_UP_P
ANY, ALL
WARP_SYNC
5 ~
VOTEU_UP_P.ALL — 2 fields · 140 samples
and_base: 0xff7886
var_mask: 0x1c000000038600000000000000000000
Bits
W
Tok
Extraction
[89:87]
3
t2
pred
[82:81]
2
t1
pred
VOTEU_UP_P.ANY — 9 fields · 10 samples
and_base: 0xff0886
var_mask: 0x1c000000048203000000000000fff084
Bits
W
Tok
Extraction
[90]
1
t1
pred
[87]
1
t2
pred
[81]
1
t1
pred
[73]
1
t1
pred
[72]
1
t1
pred
[23:16]
8
t1
reg
[15:12]
4
t0
guard
[7]
1
t0
[2]
1
t0
VOTEU_UR_UP_P.ANY — 1 fields · 8 samples
and_base: 0x00000000038e01000000000000047886
var_mask: 0x1c000000000000000000000000ff0000
Bits
W
Tok
Extraction
[23:16]
8
t1
ureg
VOTEU_UR_UP_P.ALL — 2 fields · 140 samples
and_base: 0xff7886
var_mask: 0x1c000000038600000000000000000000
Bits
W
Tok
Extraction
[89:87]
3
t2
pred
[82:81]
2
t0
VOTEU.ALL
Uniform warp vote.
InsKey
Operands
Pipeline
Latency
VOTEU.ALL_UP_P
UP_P
WARP_SYNC
5 ~
VOTEU.ALL_UP_P — 4 fields
and_base: 0xff0886
var_mask: 0x1c000000078e0000000000000000f000
Bits
W
Tok
Extraction
[90]
1
t2
neg
[89:87]
3
t2
pred
[83:81]
3
t1
upred
[15:12]
4
t0
guard
VOTEU.ANY
Uniform warp vote.
InsKey
Operands
Pipeline
Latency
VOTEU.ANY_UP_P
UP_P
WARP_SYNC
5 ~
VOTEU.ANY_UR_UP_P
UR_UP_P
WARP_SYNC
5 ~
VOTEU.ANY_UP_P — 2 fields · 32 samples
and_base: 0x00000000000001000000000000ff7886
var_mask: 0x00000000018e00000000000000000000
Bits
W
Tok
Extraction
[88:87]
2
t2
pred
[83:81]
3
t1
upred
VOTEU.ANY_UR_UP_P — 5 fields
and_base: 0x886
var_mask: 0x1c000000078e00000000000000fff000
Bits
W
Tok
Extraction
[90]
1
t3
neg
[89:87]
3
t3
pred
[83:81]
3
t2
upred
[23:16]
8
t1
ureg
[15:12]
4
t0
guard
WARPSYNC
Reconverge warp after unstructured divergence.
InsKey
Operands
Modifiers
Pipeline
Latency
WARPSYNC
ALL, COLLECTIVE
WARP_SYNC
0 ~
WARPSYNC_R
R
ALL, COLLECTIVE
WARP_SYNC
0 ~
WARPSYNC_R_II
R_II
COLLECTIVE, ALL
WARP_SYNC
0 ~
WARPSYNC.ALL — 2 fields · 1 samples
and_base: 0x00000000038000000000000000007948
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[29:24]
6
t1
reg
WARPSYNC — 2 fields · 134 samples
and_base: 0x38000000000000000007348
var_mask: 0x1c00000000000000000000003f000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[29:24]
6
t1
reg
WARPSYNC.COLLECTIVE — 2 fields · 150 samples
and_base: 0x3c000000000000000087348
var_mask: 0x1c00000000000000000000001f000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[28:24]
5
t1
reg
WARPSYNC_R — 2 fields · 134 samples
and_base: 0x38000000000000000007348
var_mask: 0x1c00000000000000000000003f000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[29:24]
6
t1
reg
WARPSYNC_R.ALL — 2 fields · 1 samples
and_base: 0x00000000038000000000000000007948
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[29:24]
6
t1
reg
WARPSYNC_R.COLLECTIVE — 2 fields · 150 samples
and_base: 0x3c000000000000000087348
var_mask: 0x1c00000000000000000000001f000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[28:24]
5
t1
reg
WARPSYNC_R_II.COLLECTIVE — 2 fields · 150 samples
and_base: 0x3c000000000000000087348
var_mask: 0x1c00000000000000000000001f000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[28:24]
5
t1
reg
WARPSYNC_R_II.ALL — 2 fields · 1 samples
and_base: 0x00000000038000000000000000007948
var_mask: 0x1c000000000000000000000000000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[28:24]
5
t1
reg
WARPSYNC_R_II — 2 fields · 134 samples
and_base: 0x38000000000000000007348
var_mask: 0x1c00000000000000000000003f000000
Bits
W
Tok
Extraction
[122]
1
t1
reuse
[29:24]
6
t1
reg
WARPSYNC.ALL
Reconverge warp after unstructured divergence.
InsKey
Operands
Pipeline
Latency
WARPSYNC.ALL_?
?
WARP_SYNC
0 ~
WARPSYNC.COLLECTIVE
Reconverge warp after unstructured divergence.
InsKey
Operands
Pipeline
Latency
WARPSYNC.COLLECTIVE_R_II
R_II
WARP_SYNC
0 ~
2 partial encodings — operand types not fully identified
1 partial encoding — operand types not fully identified
InsKey
Operands
Pipeline
Latency
YIELD_?
?
CTRL_FLOW
0 ~
SM120 Instruction Set Architecture Reference — revision from sm120.json
1811 instruction forms · 2558 encoding variants · 37 pipeline classes
Reverse-engineered for interoperability under EU Directive 2009/24/EC Art. 6 and US DMCA §1201(f) github.com/kacper-daftcode/blackwell-isa